SOI MOS field effect transistor

Details SOI MOS field effect transistor SOI MOS field effect transistor

1997-12-03

2001-03-20

Hardy, David (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000, C257S350000, C257S404000

Reexamination Certificate

active

06204534

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a SOI MOS (Silicon-On-Insulator Metal Oxide Semiconductor) field effect transistor, namely, to a semiconductor device realized on a SOI substrate. More particularly, the present invention relates to an improvement of SOI MOS field effect transistor (called hereunder, MOSFET), which is applicable to integrated circuits.
2. Description of the Related Arts
SOI MOSFETS fabricated on SOI substrates like SOS (Silicon On Sapphire), SIMOX (Silicon Separation by Ion Implantation of Oxygen) and BSOI (Bonded SOI) offer advantages in low-voltage and high-speed operation. Additionally, SOI MOSFETs result in smaller layout area as compared with devices fabricated on bulk Si. On the other hand, SOI MOSFETs have only three terminals (gate, drain, and source), while the bulk Si devices require four terminals (gate, drain, source, and substrate). Because of this fact, the SOI MOSFET operates as a floating body device.
FIGS.
4
(
a
) and
4
(
b
) show schematic cross sections of MOSFETs of prior art Example 1 and their equivalent circuits. FIG.
4
(
a
) shows a schematic cross section of a SOI NMOSFET and its equivalent circuit, while FIG.
4
(
b
) shows a schematic cross section of a Bulk NMOSFET and its equivalent circuit.
Also, the equivalent circuits shown in FIGS.
4
(
a
) and
4
(
b
) show a parasitic bipolar NPN transistor and include an impact ionization current generator Ii.
In the case of the Bulk MOSFET, the bipolar transistor base terminal B is tied to the substrate terminal B, the substrate/source junction is reverse biased and, as a result, the bipolar transistor has very little effect on the MOSFET operation.
In the SOI MOSFET, the parasitic bipolar base is the transistor body (floating). In normal operation, impact ionization current generated at the drain junction could act as a base current for the parasitic bipolar transistor, creating a positive feedback effect and degrading device electrical characteristics, specially short-channel effect and reduction of the drain/source breakdown voltage. This parasitic bipolar effect imposes a serious limitation for device integration.
For SOI MOSFETS with sub-halfmicron feature sizes (channel length<0.35 &mgr;m), drain/source breakdown voltage of approximately BVdss~2.5 V is typical. As a result, the maximum supply voltage should be Vddmax~2 V. This limitation prevents the use of these SOI MOSFETs for Vdd~3 V.
Possible methods to overcome this limitation are as follows.
In the case of SOI MOSFETs according to the prior art Example 1, the method involves constructing the SOI MOSFETs on thicker top Si film and using body contacts to tie the channel region to a fixed potential. This behaves as a bulk Si device suppressing the floating body effect and the parasitic bipolar effect, thereby preventing the decrease in the breakdown voltage between the source and the drain.
As a prior art Example 2, a MOSFET is proposed which is disclosed in Japanese Unexamined Patent Publication (Kokai) No. Hei 5-218425.
FIGS.
5
(
a
) shows a schematic cross section of the MOSFET according to the prior art Example 2; and FIG.
5
(
b
) is a graph showing drain current-voltage characteristics. This device can be described by the series connection of two SOI MOSFETs with the common drain (
13
in FIG.
5
(
a
)) electrically floating. The channel length of each MOSFET is d, as indicated in FIG.
5
(
a
).
More specifically, the device comprises an active layer on an insulator film
12
formed on a silicon substrate
11
. The active layer comprises an N-type active region (floating N-type region)
13
and P-type active regions
14
,
15
sandwiching this N-type active region
13
. Of the electron-hole pairs generated near the junction of the N-type drain region
19
, the carriers bearing the P-type are injected into the N-type active region
13
. Since the impurity concentration of the N-type active region
13
typically is lower by four orders of magnitude than that of the N-type source region
18
, the amount of reverse-injected N-type carriers is extremely suppressed. The reference numerals
17
,
20
,
21
,
22
represent a gate electrode, an insulator film, a source electrode, and a drain electrode, respectively.
Therefore, the MOSFET according to prior art Example 2 suppresses deterioration of the breakdown voltage between the source and drain regions due to parasitic bipolar effect. FIG.
5
(
b
) shows drain current-voltage characteristics (Id-Vds characteristics) when the gate lengths are adjusted so that L
1
=L
2
=0.35 &mgr;m in the construction of a MOSFET shown in FIG.
5
(
a
).
As a prior art Example 3, a MOSFET is proposed which is disclosed in M. H. Gao et al.: “Dual-MOSFET structure for suppression of kink in SOI MOSFETs at room and liquid helium temperatures”, 1990 IEEE SOI Conference, pp. 13-14.
FIGS.
6
(
a
) to
6
(
d
) are views showing a schematic cross section, a layout, and drain current-voltage characteristics of the MOSFET according to the prior art Example 3. Basically, two transistors are connected in series, then electrically, this configuration is equivalent to that of the MOSFET shown in FIG.
5
(
a
).
More specifically, FIG.
6
(
a
) is a view showing a schematic cross section of the dual device in which two NMOSFETs are connected in series. FIG.
6
(
b
) is a plan view showing a layout of the dual device. FIG.
6
(
c
) is a view showing drain current-voltage characteristics of a single device (in dotted line) and drain current-voltage characteristics of a dual device (in solid line).
The “kink” effect is a sudden increase in the drain saturation current Id at a certain source-drain voltage Vds relative to the input gate voltage Vgs, as shown by the drain current-voltage characteristics in dotted line of FIG.
6
(
c
). The “kink” effect appears when the top channel adjacent to the drain enters the source-drain punchthrough regime.
In the drain current-voltage characteristics shown by the solid line of FIG.
6
(
c
), the “kink” effect is reduced by increasing the channel length of one of the transistors.
FIG.
6
(
d
) shows drain current-voltage characteristics when the gate lengths of the two elements are adjusted so that L
1
=0.8 &mgr;m and L
2
=0.35 &mgr;m. As shown, the “kink” effect (kink current) in the drain current-voltage characteristics is reduced.
However, the SOI MOSFET device structures of the prior art Examples 1 to 3 described in the previous section have limitations that restrict the use in high density integrated circuits.
(1) In the prior art Example 1, SOI MOSFETs fabricated on thick top Si film degrades short channel effects. Furthermore, the need for a body contact complicates the layout and increases device area.
(2) The MOS transistor of FIG.
5
(
a
) according to prior art Example 2 is difficult to implement for minimum size submicron channel length devices.
2-1) For 0.35 &mgr;m gate length device, the channel length of each P-type region
14
and
15
would be d~0.1 &mgr;m. This length is very much comparable to the lateral diffusion of N
+
-type impurity. Therefore, control is extremely difficult and electrical characteristics are liable to have a large variation.
2-2) Furthermore, for this kind of MOSFET according to the prior art Example 2 with the same channel lengths (L
1
=L
2
=0.35 &mgr;m) for P-type regions
14
and
15
and the threshold voltage ratio being set to have Vth
1
/Vth
2
=1, it is experimentally found that there is a very large “kink” current generated in the drain current-voltage characteristics, as illustrated in FIG.
5
(
b
).
(3) In the prior art Example 3, the “kink” effect can be greatly reduced by adjusting the channel lengths of the transistors of the dual element, as shown in FIG.
6
(
b
). This is due to the fact that the transistor driving current is reduced since Id decreases as the channel length grows larger. However, since the gate lengths for this structure are such that L
1
/L
2
=0.8 &mgr;m/0.35 &mgr;m, there is a problem that,

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