Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-06
2003-07-22
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S407000
Reexamination Certificate
active
06596570
ABSTRACT:
DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of silicon-on-insulator (SOI) field effect transistors (FETs); more specifically, it relates to an SOI FET having reduced junction area capacitance and the method of fabricating said device.
2. Background of the Invention
In SOI technology, a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn, is formed over a substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply BOX. Transistor source and drains are formed, for example, by ion implantation of N and/or P dopant into the thin silicon layer with a body region between the source and drain. Gates are formed on top of the body region, for example, by deposition of a gate dielectric and conductor on a top surface of the thin silicon, followed by, photolithographic patterning, and etching.
FETs built in SOI technology have significant advantages over FETs built using bulk silicon technology. Among the advantages of SOI technology are reduced short channel effects, lower parasitic capacitance and increased drain on-current. However, as SOI FET dimensions are downscaled ever smaller to take advantage of, for example, reduced area junction capacitance of downscaled devices increases as the BOX is downscaled (thinned). Increased area junction capacitance causes device performance degradation.
Turning to
FIG. 1
,
FIG. 1
is a partial cross-sectional view of an SOI FET illustrating the various active and parasitic capacitors. FET
100
comprises a silicon substrate
105
, a BOX
110
formed on top of the substrate, and a thin silicon layer
115
, formed on top of the BOX. FET
100
further comprises source/drains
120
formed in silicon layer
115
and a body region
125
, also formed in the silicon layer, separating the source/drains. FET
100
still further comprises a gate dielectric
130
, a gate conductor
135
, and sidewall spacers
140
formed on sidewalls
145
of gate conductor
135
. Extending from a top surface
150
of silicon layer
115
, through the silicon layer, to BOX
110
is shallow trench isolation (STI)
155
.
The active and parasitic capacitors are located as follows. A front-gate capacitor
160
exists between gate conductor
135
and body region
125
. The dielectric for front-gate capacitor
160
is gate dielectric
130
. Area junction capacitors
165
exist between each source/drain
120
and substrate
105
. A back-gate capacitor
170
exists between body region
125
and substrate
105
. The dielectric for area junction capacitors
165
and back-gate capacitor
170
is BOX
110
. The capacitance of each of these capacitors is given by the well-known equation:
C
=
ϵ
0
ϵ
ox
T
ox
in which C is the capacitance, É>
0
is the dielectric constant of free space, É>
0x
is the dielectric constant of the dielectric and T
ox
is the thickness of the dielectric. It is desirable for front-gate capacitor
160
to be large in order to increase the on-current and decrease the off-current. This is accomplished by either decreasing the thickness of gate dielectric
130
or by using a material with a high dielectric constant for the gate dielectric. It is desirable for area junction capacitors
165
to be small for reasons described above. However, it is desirable for back-gate capacitor
170
to be large at the same time. The reason a large back-gate capacitor
170
is desirable is to improve off-current control the threshold voltage control. Since the dielectric for area junction capacitors
165
and back-gate capacitor
170
is BOX
110
, it is apparent that it is not possible to optimize the area junction capacitors and the back-gate capacitor at the same time.
FIG. 2
is a partial cross-sectional view of a double BOX SOI FET illustrating the various active and parasitic capacitors. The purpose of
FIG. 2
is to illustrate that a double BOX SOI device still has the problem described above for a single BOX device. FET
200
comprises a silicon substrate
205
, a thick first BOX
210
formed on top of the substrate, a thin first silicon layer
215
, which is doped to about 10
18
to 10
19
atm/cm
3
, formed on top of the first BOX, a thin second BOX
220
formed on top of the first silicon layer and a thin second silicon layer
225
formed on top of the second BOX. FET
200
further comprises source/drains
230
formed in second silicon layer
225
and a body region
235
, also formed in the second silicon layer, separating the source/drains. FET
200
still further comprises a gate dielectric
240
, a gate conductor
245
, and sidewall spacers
250
formed on sidewalls
255
of gate conductor
245
. Extending from a top surface
255
of second silicon layer
225
, through the second silicon layer, through second BOX
220
, through first silicon layer
215
to first BOX
210
is STI
260
.
The active and parasitic capacitors are located as follows. A front-gate capacitor
265
exists between gate
245
and body region
235
. The dielectric for front-gate capacitor
265
is gate dielectric
240
. Area junction capacitors
270
exist between each source/drain
230
and first silicon layer
215
. A back-gate capacitor
275
exists between body region
235
and first silicon layer
215
. The dielectric for area junction capacitors
270
and back-gate capacitor
275
is second BOX
220
. A substrate capacitor
280
exists between first silicon layer
215
and substrate
205
. The dielectric for substrate capacitor
280
is first BOX
210
. While first BOX
210
may be thick to reduce the capacitance of substrate capacitor
280
, again, since the dielectric for area junction capacitors
270
and back-gate capacitor
275
is second BOX
220
, it is not apparent that it is possible to optimize the area junction capacitors and the back-gate capacitor at the same time.
Therefore, a method of fabricating an SOI FET having a small area junction capacitance and a large back-gate capacitance is required in order to obtain all the benefits of SOI technology when downscaling.
BRIEF SUMMARY OF THE INVENTION
A first aspect of the present invention is a semiconductor structure comprising: a dielectric layer, the dielectric layer having a first and a second region, the first dielectric region having a first dielectric constant and the second dielectric region having a second dielectric constant different from the first dielectric constant.
A second aspect of the present invention is an SOI FET comprising: a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region, the undoped region having a dielectric constant different from a dielectric constant of the doped regions; source/drains in the silicon layer and separated by a body in the silicon layer, the source/drains aligned over the doped regions and the body aligned over the undoped region; and a gate dielectric on top of the body and a gate conductor on top of the gate dielectric.
A third aspect of the present invention is a method of fabricating a semiconductor structure comprising: providing a dielectric layer; forming a first region in the dielectric layer, the first region having a first dielectric constant; and forming a second region in the second dielectric, the second region having a second dielectric constant different from the first dielectric constant.
A fourth aspect of the present invention is a method of fabricating an SOI FET comprising: providing a silicon substrate having silicon layer on top of a buried oxide layer; forming a gate dielectric on top of silicon layer; forming a gate conductor on top of the gate dielectric; forming source/drains in the silicon layer; the source drains separated by a body in the silicon layer, the body aligned under the gate; and forming doped regions in the buried oxide layer, the doped regions aligned under the source/drains and having a dielectric constant different from a dielectric constant of non-doped regions of the buried oxide layer.
REFERENCES:
patent: 4717677 (
Fourson George
Henkler Richard A.
Schmeiser Olsen & Watts
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