Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-06-14
2005-06-14
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S154000, C438S217000
Reexamination Certificate
active
06905918
ABSTRACT:
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.
REFERENCES:
patent: 4199773 (1980-04-01), Goodman et al.
patent: 5024965 (1991-06-01), Chang et al.
patent: 5164805 (1992-11-01), Lee
patent: 5166765 (1992-11-01), Lee et al.
patent: 5231045 (1993-07-01), Miura et al.
patent: 5315144 (1994-05-01), Cherne
patent: 5501993 (1996-03-01), Borland
patent: 5599728 (1997-02-01), Hu et al.
patent: 5614433 (1997-03-01), Mandelman
patent: 5942781 (1999-08-01), Burr et al.
patent: 6037617 (2000-03-01), Kumagai
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6503783 (2003-01-01), Mouli
patent: 6635928 (2003-10-01), Mouli
patent: 6716682 (2004-04-01), Mouli
patent: 2002/0089032 (2002-07-01), Huang
Heemyong Park, Erin C. Jones, Paul Ronsheim, Cyril Cabral, Jr., Chris D'Emic, Guy M. Cohan, Ralph Young and Werner Rausch, “Dopant Redistribution in SOI during RTA: A Study on Doping in Scaled-down SI Layers”,IEEE,1999, pp. 14.2.1 to 14.2.4.
A.1.3.2 Spurious Effects in Sub-Micron MOSFETs, http://www.iue.tuwien.ac.al/diss/schrom/diss
ode90.html.
2.7.2 Threshold Control, http://www.iue.tuwien.ac.al/diss/schrom/diss
ode26.html.
Random discrete dopant fluctuation: Ultra-thin channel SOI, http://www.research.ibm.com/0.1um/pwong.html.
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