Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-12-20
2004-07-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S149000, C438S311000, C438S516000
Reexamination Certificate
active
06764917
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to forming silicon on insulator devices having improved characteristics.
BACKGROUND OF THE INVENTION
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS device includes a bulk semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS device is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
As an alternative to forming a MOS device on a bulk semiconductor substrate, the semiconductor layer can be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. This technology is referred to as Silicon-on-Insulator (SOI) technology. Silicon on insulator materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. For example dielectric isolation and reduction of parasitic capacitance improve circuit performance. Compared to bulk circuits, SOI is more resistant to radiation. For example, silicon-on-sapphire (SOS) (SOS) technology has been successfully used for years to fabricate radiation-hardened complimentary MOS (CMOS) circuits for military applications. Circuit layout in SOI can also be greatly simplified and packing density greatly increased if the devices are made without body contacts in which the body regions of these devices are “floating”.
A disadvantage of many SOI devices is the lack of a bulk silicon or body contact to the MOS transistor. If the channel/body region is left “floating”, various hysteresis effects can prevent proper circuit operation. These effects include the so-called “kink” effect and the parasitic lateral bipolar action. Partially-depleted devices are such that the maximum depletion width in the body is smaller than the thickness of the semiconductor Si layer, and a quasi-neutral region results which has a floating potential. These floating body effects may result in undesirable performance in SOI devices.
MOS devices using SOI structure typically fall in one of two groups depending on the type of dopants used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
One consideration when manufacturing NMOS and PMOS SOI transistors is maintaining a proper channel length. The channel length can be shortened, for example, if the source/drain regions are exposed to excessive temperature and/or time during activation. This causes excess lateral diffusion of the dopants, which causes the channel length to shorten. NMOS and PMOS transistors are formed on a single chip and are therefore exposed to the same temperature/time profile during dopant activation. However, because the NMOS and PMOS transistors are formed using different dopants, which likely have different diffusion characteristics, the temperature/time profile for at least one of the NMOS or PMOS transistors will not be optimized.
Another consideration when forming transistors on a SOI structure is the formation of both fully depleted and partially depleted transistors. In a fully depleted transistor, the source/drain regions extend all the way through the silicon layer to the insulator, and in a partially depleted transistor, the source/drain regions extend partially through the silicon layer. One difference between a partially depleted transistor and fully depleted transistor is that the threshold voltage to obtain a drive or on current through a fully depleted transistor is lower than the threshold voltage for a partially depleted transistor. Accordingly, a need exists for an improved method of forming devices on an SOI structure that allows for improved performance, minimization of floating body effects, and allows for separate optimization of separate transistors formed on the SOI structure.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device that improves performance, minimizes floating body effects, and allows for separate optimization of separate transistors formed on an SOI structure. The method includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer can initially have the same thickness.
In another aspect of the invention, the first portion of the silicon layer is partially removed by etching. The partial removal of the first portion of the silicon layer can also include depositing a resist over the silicon layer and exposing and developing the resist to expose the first portion of the silicon layer. The thickness of the first portion is determined by etching the first portion for a predetermined length of time.
In still another aspect of the invention, the first portion of the silicon layer is partially removed by oxidizing the first portion of the silicon layer and removing the oxidized silicon. The partial removal of the first portion of the silicon layer can also include depositing a mask layer and a resist over the silicon layer and exposing and developing the resist to expose a portion of the mask layer over the first portion of the silicon layer and removing the mask layer over the first portion of the silicon layer. After partially removing the first portion, the mask layer can then be removed.
Isolating features can be formed before or after the first portion of the silicon layer is partially removed. Also, a first transistor can be formed in the first portion and a second transistor can be formed in the second portion. The first transistor can be a fully depleted transistor, and the second transistor can be a partially depleted transistor. Also, the first transistor can include source/drain regions formed with a first dopant and the second transistor can include source/drain regions formed with a second dopant, and the diffusivity of the second dopant into silicon is greater than the diffusivity of the first dopant into silicon.
In another embodiment of the present invention, a sem
Chan Darin A.
En William G.
Michael Mark W.
Pellerin John G.
Advanced Micro Devices , Inc.
Nelms David
Nguyen Dao H.
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