Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-16
2002-11-12
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S352000, C257S353000, C257S354000
Reexamination Certificate
active
06479865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon-on-insulator(“SOI”) device and a method of fabricating the same, particularly to an SOI device and the method of fabricating the same capable of preventing from generating leakage current at edges of an active region.
2. Description of the Related Art
As the semiconductor device has progressed with highly enhanced performance, there has been watched a semiconductor integration technology employing, instead the silicon substrate of bulk silicon, an SOI substrate of stack structure consisting of a base substrate, a buried oxide layer and a semiconductor layer. This is because the device formed on the SOI substrate(hereinafter “an SOI device”) compared to the conventional device, has advantages likewise faster operation speed due to small junction capacitance, lower voltage due to low threshold voltage and a latch-up removal due to a complete device isolation.
Meanwhile, an isolation step during the manufacturing process of the SOI device for defining active regions is conducted as the LOCOS method or the trench method. In addition, the isolation step is also conducted as the MESA isolation method that a semiconductor layer corresponding to a field region is etched to the buried oxide layer.
Hereinafter, an SOI device and a method of fabricating the same obtained according to the MESA isolation method will be described with reference to
FIGS. 1 and 2
. Herein,
FIG. 1
is its plane view, and
FIG. 2
is a cross-sectional view taken along the line II-II′ of
FIG. 1
to illustrate the fabricating method.
Referring to
FIG. 1
, an active region AR is defined by etching a semiconductor layer portion
3
corresponding to a field region FR so that the active region AR is formed in shape of an island. A gate electrode
12
is provided in shape of lines, and active regions neighboring in their vertical or horizontal directions are interconnected by the gate electrode
12
.
Referring to
FIG. 2
, an SOI substrate
10
of stack structure consisting of a base substrate
1
, a buried oxide layer
2
and a semiconductor layer
3
is provided. The SOI substrate
10
includes an active region AR and a device isolation region FR, the active region AR is defined by etching a semiconductor layer portion corresponding to the field region FR to a buried oxide layer
2
. A gate electrode
12
having a gate oxide layer
11
is formed on a resultant such that the gate electrode
12
covers the edges of the active region AR.
However, the conventional SOI device manufactured according to the MESA isolation method increases leakage current because the gate electrode surrounds edges of the active region AR. As a result, operation speed of the device is degraded.
More particularly, the conventional SOI device manufactured according to the MESA isolation method as shown in
FIG. 2
is formed in the shape that the gate electrode surrounds edges of the active region AR. In this case, when a selected voltage is applied to the gate electrode
12
, an electric field owing to the gate electrode
12
is concentrated onto the edges of the active region AR. However, the concentration at the edges of the active region AR causes a phenomenon that a channel formed at edges of the active region AR is turned-on earlier than a channel formed inside the active region. As a result, the off-leakage current is increased, thereby degrading the device property.
FIG. 3
is a graph showing VG-ID curve of the above-identified SOI device. In the drawing, the full-line is a real VG-ID curve including the edge effect, and the dotted line is a VG-ID curve excluding the edge effect.
Referring to
FIG. 3
, there is appeared a hump since the channel formed at edges of the active region AR is turned-on earlier than the channel formed inside the active region. In comparison of the off-leakage current at V
GS
=0 V, the leakage current on a certain occasion occurring the edge effect, is greater than that of the leakage current on an occasion not occurring the edge effect.
Therefore, when an SOI device is formed according to the MESA isolation method, the essential objective to be solved is to prevent increase of the leakage current due to the edge effect so that the degradation of the device property is prevented.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide an SOI device having no edge leakage current.
It is another object of the present invention to provide a method of fabricating an SOI device having no edge leakage current.
An SOI device to accomplish the foregoing objectives includes: an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; an oxide layer formed to be in contact with the buried oxide layer at the semiconductor layer portion corresponding to a field region so that an active region is defined; a gate electrode pattern having a gate oxide layer, the gate oxide layer only formed on the active region; a source region and a drain region formed inside the active region of the semiconductor layer of both sides of the gate electrode pattern; and a gate electrode line formed on the gate electrode pattern and on the field region so as to interconnect the gate electrode patterns of the respective active regions arranged in a line.
The method of fabricating the SOI device according to the object of the present invention includes the steps of: providing an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; forming successively a gate oxide layer and a first conduction layer on the semiconductor layer; etching the gate oxide layer portion, the gate oxide layer corresponding to a field region and the gate oxide layer so that an active region is defined; depositing an oxide layer on a resultant; polishing the oxide layer until the etched first conduction layer is exposed; depositing a second conduction layer on the etched first conduction layer and on the polished oxide layer; forming a mask pattern in shape of a line on the second conduction layer; forming a gate electrode pattern only formed on the active region by etching the second conduction layer, the etched first conduction layer and the gate oxide layer with using the mask pattern, and a gate electrode line interconnecting the gate electrode patterns of the respective neighboring active regions arranged in a line; and forming source and drain regions inside the semiconductor layer portions of both edges of the gate electrode line.
Moreover, another method of fabricating the SOI device according to the objective of the present invention includes the steps of: providing an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; forming successively a gate oxide layer and a first conduction layer on the semiconductor layer; patterning the first conduction layer and the gate oxide layer to form a conduction line; forming source and drain regions inside the semiconductor layer portions of both sides of the conduction line; etching the conduction line having the gate oxide layer on a field region and the semiconductor layer to define an active region, thereby forming a gate electrode pattern only on the active region; depositing an oxide layer on a resultant; polishing the oxide layer until the gate electrode pattern is exposed; and forming a gate electrode line interconnecting gate electrode patterns formed at the respective neighboring active regions arranged in a line.
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Lee Won Chang
Lee Woo Han
Flynn Nathan J.
Hyundai Electronics Industries Co,. Ltd.
Pillsbury & Winthrop LLP
Sefer Ahmed N.
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