SOI CMOS dynamic circuits having threshold voltage control

Details SOI CMOS dynamic circuits having threshold voltage control SOI CMOS dynamic circuits having threshold voltage control

2000-03-17

2002-08-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000

Reexamination Certificate

active

06433587

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electronic circuits implemented in SOI CMOS. Specifically, dynamic CMOS circuits are described where each circuit device has a threshold voltage which is controlled to reduce threshold variations.
CMOS circuits may be implemented as partial depletion SOI circuits which constitute logic circuits for producing a voltage on a node characterizing the logical combination of logic input signals. A clock signal controls two phases of operation, a precharge phase in which the node is set to the logical value which is a function of input conditions, and an evaluate stage wherein an output voltage representing the logic value is produced.
In partially depleted SOI CMOS circuit implementations, certain bipolar effects and history effects are experienced. The bipolar effects occur when a device connected to the charge node assumes a body potential which can result in bipolar current conduction during the evaluate phase, changing the node voltage and otherwise destroying data represented by the node voltage. History effects represent changes in the data propagation delay of the circuit which are significantly influenced by the change in transistor gate to source voltage thresholds. The gate to source voltage thresholds change as the device body voltage increases during the precharge phase. As the SOI body voltage of an NFET increases, the threshold voltage for the device decreases, varying the switching point. The change in threshold not only produces a change in device delay, it also produces changes in noise immunity. As the threshold voltage decreases the noise immunity for the device correspondingly decreases.
The present invention is directed to a circuit which inhibits charging of the transistor body potential in dynamic circuit applications, particularly in the partial depletion SOI CMOS environment.
SUMMARY OF THE INVENTION
A dynamic CMOS circuit is provided which produces a voltage on a charged node representing a logical function applied to input logic signals. The dynamic circuit is clocked with a clock input signal to establish a logical output for the circuit. The input transistors of the circuit which receive the logic input signals have a body contact which is connected to a voltage potential through a switching transistor so that during the precharge phase, the body potential of the input transistors is maintained at a constant reference voltage level. When the circuit enters the evaluate stage, the switching transistor is rendered into a non-conducting condition, and the body potential is permitted to float from its preestablished voltage level, and the node is charged to a value representing the logical function applied to the input signal conditions.
By pre-establishing a reference voltage level Vss on the body contact, the threshold voltage for the device remains substantially constant, and the delays through the circuit are stabilized. Additionally, by maintaining the body contact potential at a known level near the source potential, bipolar effects are minimized which would otherwise effect the node potential and corrupt the data represented by the node voltage.


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