SOI circuit design method

Details SOI circuit design method SOI circuit design method

2000-03-15

2002-08-27

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06442735

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit design and, more particularly, to methods of simulating and designing silicon on insulator integrated circuits.
2. Background Description
In recent years silicon on insulator (SOI) technology has become the main force for performance improvement for transistors in addition to scaling. SOI transistors may be formed on the surface of a silicon layer isolated from a silicon substrate by a buried oxide (BOX) layer. In a typically complex series of mask steps, shallow trenches filled with oxide isolate SOI islands of the surface silicon layer on which circuits are formed. Device channels may be allowed to float or, if desired, local contacts may be made to each of the circuit's conduction wells and at least one body contact may be made to the silicon layer island. For many circuits it may be sufficient to form a single body contact to a p-type silicon island layer at a common point with n-type field effect transistors (NFETs) distributed around the island. Normally, slight variations in device characteristics such as device thresholds, are negligible, neglectable and not given much consideration for typical logic circuits such as sense amplifiers, decoders, clock buffers, input or output drivers and array output drivers.
However, to further increase device density and improve performance, body contacts are eliminated or shared by larger and larger numbers of devices. As the body contact density is reduced while device density increases, individual devices become much more susceptible to localized heating and what is known as body effects.
Body effects occur especially in analog logic circuits, memories or logic where the SOI body layer contacts may be infrequent or, in devices with completely isolated (i.e., no body contact) floating device channels. As a particular device switches, charge is coupled into/out of the channel body. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated locations as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates and, eventually, the injected charge reaches some steady state value that acts as a substrate bias for the device.
Localized heating occurs because these electrically isolated devices are thermally isolated as well. Devices dissipate power during switching that is dependent upon device switching current. In a typical non-SOI technology, heat would dissipate through an underlying silicon substrate or through metal connections above. However, for SOI self heating within a device does not dissipate immediately because of the additional thermal isolation. Over time, as the device is heated and re-heated, residual heat elevates that device's steady state temperature above other less active devices on the same chip/circuit.
FET device characteristics, including threshold voltage (V
t
) and device currents, are dependent upon device substrate voltage (V
sx
) and temperature. So, localized temperature and body effect variations cause device non-uniformity. Further, since these localized differences are zero, initially, and build up with time as the circuit operates, circuit characteristics for identical circuits also vary with time. These variations can cause circuit malfunctions that are difficult to diagnose and find, much less anticipate during design.
These variations are especially troublesome for memory chips or macros with large arrays of memory cells, such as Random Access Memory (RAM) chips. A Static RAM (SRAM) is, essentially, an identical pair of cross coupled transistors loaded with high resistance load resistors and a pair of pass transistors between internal storage nodes and a pair of bit lines. The state of the cross coupled pair determines the state of data stored in the cell. Each SRAM cell is read by coupling the cross coupled transistors through the access transistors to the bit line pair and measuring the resulting voltage difference on the bit line pair. The signal on the bit line pair increases with time toward a final state wherein each one of the pair may be, ultimately, a full up level and a full down level. However, to improve performance, the voltage difference is sensed well before the difference reaches its ultimate value.
A Dynamic RAM (DRAM) cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Each DRAM cell is read by coupling the cell's storage capacitor (through the access transistor) to a bit line, which is a larger capacitance, and measuring the resulting voltage difference on the bit line. Typically, the bit line signal is a few hundred millivolts (mv) that develops asymptotically from the time that the access transistor is turned on dependent upon the overall RC time constant of the signal path.
Repetitively accessing a cell induces local effects in the cell. Localized effects that, increase thresholds and reduce device currents, can reduce the charge stored in DRAM cells and reduce the voltage passed by access transistors. These local effects can cause an imbalance in the cross coupled pair devices in an SRAM cell, or local effects in pass gates of an SRAM cell cause an apparent imbalance. Further, local effects can increase path resistance which increases the cell write time (i.e., the time required to store the charge in the DRAM cell or to switch the state of the cross coupled pair in the SRAM cell) and increases cell sense time, i.e., the time required to develop sufficient signal to sense. As a result, intermittent problems may arise, such as spuriously in sensing the wrong data.
Furthermore, to achieve high DRAM performance, state of the art sense amplifiers, typically a pair of cross coupled transistors, must sense a potential difference that is something less than the ultimate few hundred millivolt signal. The smaller the potential difference that the sense amplifier can sense the better. So, any difference in the transistors in the cross coupled pair increases the necessary potential difference and, therefore, slows sensing. Therefore, it is important that the transistors in the cross-coupled pair have identical device characteristics and are what is known as a balanced or matched pair. As a consequence, great care is taken in designing a balanced pair to insure that each transistor is influenced by ambient conditions identically with the other of the pair.
However, other constraints may further complicate the task of designing a matched pair of transistors. For example, each sense amplifier may be constrained to fit on the same pitch as a pair of adjacent bit lines, each pair of adjacent bit lines being coupled to a corresponding sense amplifier. In this example in addition to other constraints, the cross coupled transistor pair must fit in a very narrow pitch. This narrow pitch further complicates transistor design placement (layout) to achieve a balanced pair, especially for SOI circuits. Localized effects occurring on only one of the balanced pair of FETs may reduce the original design noise margin enough to make a particular sense amplifier useless. Further, localized effects in a balanced sense amplifier pair may be exhibited as a pattern dependent or sporadic failure, making it very difficult to diagnose.
FIG. 1
shows a typical body effect model
100
for a single NFET, which is modeled as a capacitive voltage divider including capacitors between a device channel or body node
102
and each of device nodes, source
104
, drain
106
and gate
108
and a node
110
representing an underlying substrate layer. Device source/drain diffusions are represented by a pair of back to back diodes each between one of the source
104
or drain
106
and the body node
102
. This prior art model
100
is adequate fo

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