Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-06-12
2002-06-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S238000
Reexamination Certificate
active
06410369
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to silicon-on-insulator (SOI) devices and, more particularly, to an SOI body having a selective equilibration link.
An electric potential of a floating silicon-on-insulator (SOI) body depends upon its present bias state and also on its history. An alpha particle hit to the SOI body can also significantly alter the body-charge state. Consequently, it may be impossible to maintain closely matched threshold voltages (Vts) in circuits requiring the condition of closely matched Vts. Since the potential of a floating SOI body depends on its present bias state and also on its history, circuits such as latch type sense amplifiers of any memory cell. A latch type sense amplifier may experience serious Vt mismatch, which adversely affects a performance of the circuit. For example, for a sense latch requiring closely matched Vts in the cross-coupled devices, due to the dependence of body charging on device state, Vt mismatches up to 300 mV are likely to occur. The uncontrollable Vt mismatch degrades the ability of the sense amplifier to detect small signals. For SRAM cells, alpha particle induced Vt mismatch has been observed to disturb an SOI body more than bulk CMOS designs.
To illustrate the problem of Vt mismatch, let us now refer to
FIGS. 1A-1C
in which a cross-coupled NFET pair
10
of a sense amplifier is shown at various times or phases of operations. During a “latched phase”, the body of the device
12
on the left (condition 1, Vg=0 V, Vd=2.0 V, Vs=0 V) will charge with holes as a result of impact ionization and thermal generation (FIG.
1
A). Full body charging typically occurs within 10-20 ns. The device
14
on the right (condition 2, Vg=2.0 V, Vd=Vs=0 V) will have the body in a maximally depleted condition of (minimum) holes. Since the cross-coupled NFETs
10
may sit (i.e., remain) in these states for times much longer than 20 ns, a significant difference in body charge and potential is developed.
FIG. 2
shows hole concentration contours for the device
12
of
FIG. 1A
in condition 1, as modeled using a device simulation/modeling tool, as is known in the art. Note that the maximum hole concentration is greater than 1 ×10
17
, which in this instance is approximately equal to the background doping concentration. On the other hand, the device
14
of
FIG. 1A
in condition 2 (referring now to
FIG. 3
) is essentially fully depleted. The peak hole concentration is approximately 1×10
12
, which is negligible relative to the background doping concentration. The restore phase (
FIG. 1B
) does not last long enough for the body charge to equilibrate to equal values, although the electrical bias is equal on each device. Typically, it takes hundreds of milliseconds for equilibration to occur, since hole charge decreases by recombination and current through the source; both are very slow processes in comparison with the setting of a sense amplifier for a sensing operation. Once a new setting phase (
FIG. 1C
) is entered (also referred to as a triggering and/or activating of the sense amplifier), the devices still have a maximum body-charge mismatch condition and have different threshold voltages. A body-charge mismatch resulting from the latched phase results in a Vt mismatch during the setting phase. As shown, body
14
of
FIG. 1C
experiences a transition in source voltage from 2.0 volts to 1.0 volt.
FIG. 4
is a comparison of modeled Id−Vs characteristics during the setting phase for the devices
12
,
14
in condition 1 and condition 2, respectively, as shown in
FIG. 1C
after the restore phase. Note that an apparent Vt mismatch of approximately 135 mV exists for this example, which detracts from the ability to sense small signals on the order of 8-250 mV of the sense amplifier of an SOI memory cell.
In another example, consider the schematic of a typical latch type sense amplifier
20
, such as shown in FIG.
5
. The procedure for reading from a cell
22
shall now be briefly described. First, the bit lines, BLC (Complement bit-line) and BLT (True bit-line), are precharged by a sense amplifier reset/restore signal (SMPRST), used to charge both bit lines to a certain level prior to a read/write operation. The cell
22
may then be read by activating its wordline (WL), which develops a small offset voltage between the paired bitlines BLC and BLT. After a predetermined delay, a set signal (SET) is activated and the cross-coupled inverters (N
1
/P
1
, N
2
/P
2
) latch the signal (i.e., the two inverters latch a particular state and then remain in that state). Finally, the “0” and “1” signals are sent out through data out drivers (not shown) connected to the bitlines.
The delay of the set signal (SET) is critical for proper setting of the latch and for sense amplifier performance. If the sense amplifier
20
is set too early, erroneous data could be received as a result of insufficient time for allowing the data to propagate through the longest path of the data through the SRAM device. However, if the set pulse occurs too late, the cost is extra delay added to the read cycle of the SRAM device. Normally, for today's SRAMs, the set signal is fired when the bitline offset voltage reaches about 150 mV.
For SOI devices, since all the bodies are floating, the initial body potential can range from near ground to near Vdd (when considering both NFETs and PFETs whose source may not necessarily be grounded or tied to Vdd). As referred to herein above, this produces a large Vt mismatch. This mismatch can slow down sensing (i.e., a slower set pulse is required) or it results in a complete failure to set the latch in a proper direction.
Circuit simulations of SOI devices have been performed for initial body potential mismatches up to 700 mV using a suitable circuit simulation tool, as is known in the art. Referring now to
FIG. 6
, a simulation of sense amplifier operating margin is shown. Curve A shows a required bitline offset voltage for reliable sensing as a function of body potential mismatch for separate, non-linked adjacent NFET bodies. In this instance, the set signal must be delayed by approximately a factor of three (3) relative to invoking the set pulse at a bitline offset of 100 mV. Simulations have also shown that if the set signal is triggered at a 150 mV bitline differential, only 400 mV or less of body potential mismatch can be tolerated. Any body potential mismatch above 400 mV cannot be tolerated.
The role of alpha particles and impact ionization generated charge shall now be discussed. It has been observed that alpha particle radiation results in significantly increased soft error rate (SER—corresponding to an error rate resulting from alpha particle bombardment) for SOI type SRAM cells relative to cells fabricated in bulk CMOS, especially with an applied voltage greater than 1.75 V (see FIG.
7
). SOI has inferior SER immunity relative to bulk silicon devices at voltages greater than 1.75 V due to floating-body bipolar amplification of impact ionization charge initiated by the alpha particle hit. Note, however, at lower voltages, amplification of impact ionization generated charge in SOI is less of a factor and SOI is superior at lower voltages to bulk because of its smaller capture cross-section. In other words, at low voltages SOI is superior because of reduced significance of impact ionization and smaller capture cross-section. The soft error fails (i.e., failures) are amplified also by Vt mismatch caused by uneven (i.e., non-uniform) body charge generation of a cross-coupled latched sense amplifier. It is thus desirable to provide a method and apparatus to enhance SOI body potential equilibrium of alpha particle generated charge under certain operating conditions and to minimize Vt mismatch caused by alpha particle generated charge.
The local sense amplifier Vt mismatch problem of a floating SOI body has not yet been recognized in the art. However, floating body problems in general have been addressed with various solutions, which includes
Assaderaghi Fariborz
Flaker Roy Childs
Flaker Scott
Hsu Louis L.
Mandelman Jack A.
Connolly Bove Lodge & Hutz LLP.
Flaker Scott
International Business Machines - Corporation
Lattin Christopher
Niebling John F.
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