SOI array sense and write margin qualification

Details SOI array sense and write margin qualification SOI array sense and write margin qualification

2001-06-01

2002-01-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S194000, C365S191000, C365S233100, C365S233500, C365S156000

Reexamination Certificate

active

06341093

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to storage devices and in particular, it relates to a testing method and system for testing the storage quality of history dependent memory array cells, namely arrays built in SOI technology.
BACKGROUND OF THE INVENTION
Conventional CMOS SRAM arrays, commonly used as cache memories in computer processor devices, comprise memory cells which are basically structured as depicted in FIG.
1
.
The cell comprises a cross-coupled pair of transistors N
1
/P
1
having reference signs
1
,
2
and N
2
/P
2
, having reference signs
3
,
4
, respectively. A differential sensing scheme (not explicitly depicted) is used with a complementary dual rail bitline and a sense amplifier circuit sensing the voltage difference between the two bitlines
12
,
14
, BLT for true, and BLC for complement, see for reference and more detail: Correale et al., “Circuit Technique for Optimizing Access Time in Static Random Access Memories”, Technical Disclosure Bulletin volume 38 n5 05-95 pp. 483-488.
A large number, up to
1024
, of such cells, as one of them is shown in
FIG. 1
, are connected to the wires BLT
12
, BLC
14
.
This structure is often referred to as one bitline. Both bitlines—connections
12
,
14
—are pre-charged to the supply voltage Vdd prior to read or write. In a read case one cell is selected via the wordline select signal WL, and as a result one of the bitline-connections BLT or BLC is then discharged through the pass devices Q
1
, or Q
2
—having reference signs
5
, and
6
—of the selected cell, respectively, according to the data stored in the cell. The cell is as small as possible to increase storage density, and therefore the current drawn from the bitline-connection through the cell is limited. The capacitance of the bitline-connection BLT and BLC is determined mainly by the sum of the capacitance of the cell transfer devices connected to one bitline-connection plus the wire-capacitance of the connection.
In order to speed up the data access a sense amplifier circuit senses the voltage difference between the two bitlines
12
,
14
beginning at a time usually ‘long’ before one of the bitlines
12
,
14
is fully discharged.
In CMOS based memories a quite small bitline voltage difference, in the range of {fraction (1/10)} of Vdd would be sufficient to guarantee the proper function in this fully symmetric system. Several parasitic effects, however, cause asymmetries in the cell, as e.g., differences in device properties caused by different channel length, threshold voltages of the involved transistor devices, etc. Especially the pass devices Q
1
and Q
2
influence the discharge of the true and complements bitlines
12
,
14
, respectively. Coupling onto the bitlines changes the voltage differences and device properties in the sense amplifier, causing the circuit to preferably switch into one data level, e.g. logic level “0”. Thus, a certain minimum voltage difference is needed for secure reading the cell content.
In a SOI technology basically the same logical cell construction is used. The device properties of SOI-CMOS devices, however, are different from conventional bulk CMOS devices.
Thus, additional effects cause asymmetries and device performance degradation: device properties change dependent on their switching history due to the so-called body effect influencing the threshold voltages of involved transistors.
The total bitline capacitance depends on the data stored in the cells connected to the bitline because the body voltage of the cell pass devices depends on the stored data and influences the bitline loading. Further, parasitic bipolar currents slow down the discharge of the bitline, and repeated reading of a cell results in local heating as the silicon oxide to the side and the bottom thermally isolates the device. Thus, when the same reading scheme is applied as used in bulk CMOS technology the voltage difference at the sense point of the sense amplifier must compensate for all of these additional effects to guarantee the proper function of the array under operational conditions.
Prior art bulk CMOS based array hardware test methods do not have to deal with history dependent behavior. So called margins are tested and verified by extending the test conditions over the guaranteed specification. Voltage and temperature range during test is extended, access and cycle time verification is tightened. Patterns are applied which stress the neighborhood of the selected cell with respect to leakages and coupling. Such prior art array testing methods for bulk-CMOS devices are not sufficient when being applied to SOI arrays because SOI specific effects are pattern and history dependent.
The time constants of this history and pattern dependent memory effects, which alter the device properties, are in the millisecond timeframe while cycle times of modern arrays are in the nano seconds. Therefore thousands of cycles would be necessary to bring a circuit into a specific state for testing one cell which would result in an unacceptable amount of test time for a complete array with thousands or even millions of cells.
It is thus an object of the present invention to provide a reliable test method for memory arrays based on history dependent hardware, for example hardware based on SOI technology. A further objective is to implement a test facility into a SOI array memory device.
SUMMARY OF THE INVENTION
The present invention is based on the knowledge that the duration, i.e. the pulse width of the active-state of the wordline select signal, causes the voltage difference needed for evaluating the bit content when reading from the cell. More precisely, during the active state period of time the voltage difference develops in a range between the nominal voltage level for logic “0”and a full rail swing, dependent on the duration of the wordline select signal. The higher the voltage difference the more securely a bit can be read from the cell. A manipulation of the signal duration can thus be exploited for simulating rare hardware status situations in which a bit value can be read based on the history experienced during test, but the read attempt would fail with a different history, not applied during test. In the case of a write operation, the wordline select signal duration determines the time within which the cell has to flip into the state to be written to the cell. If the cell fails to switch during the time the pass devices are opened, the internal nodes fail to be overwritten with the state applied via the bitlines BLT, BLC. Thus, the cell remains in the prior state and the write function fails.
The manipulation of the wordline select signal duration, i.e. its pulse width, can now be performed basically in two different ways: first, a minimum pulse width can be found out experimentally for a given hardware which is used for testing the hardware and defines the minimum safety margin to be guaranteed by the hardware manufacturer. Then, the test may be performed at the client side with only two possible results: the hardware fulfills the quality requirements or not. Second, the pulse width can be varied systematically covering a range of pulse widths. In this case a hardware can be qualified in fine degrees which can be useful for exploring physical effects as described below.
In this way the array can be stressed selectively with predetermined test conditions which represent a read or write margin, respectively, which are able to be dimensioned such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under application conditions at the client site.
The basic idea way to achieve this is to control the sense signal developing time via the pulse width of the wordline select signal and thereby the time the cell is connected via the pass-devices to the bitline so that a voltage difference can develop on the bitlines. More particularly, shortening the pulse width is achieved by cutting off a predetermined cutoff width of the trailing edge of the pulse signal for generating a sh

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