Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-08-31
2001-11-13
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C712S227000
Reexamination Certificate
active
06317847
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data communications, and more specifically, to a system that enables a user to trace read and write accesses to registers in a data communication device.
BACKGROUND ART
The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines and intelligent communication switches create a need for data communication networks able to manage a huge amount of data at high rates. Complex software that addresses high-performance requirements of data networks is used to manage communications between a CPU and network devices.
To perform effective diagnostics of a network device, it is necessary to obtain a clear picture of interactions between a CPU and various elements of the network device. Therefore, it would be desirable to provide a system that enables a user to monitor CPU's access to various registers of a network device. To reduce CPU and system bus utilization, it would be desirable to monitor CPU's access using hardware resources of a network device.
DISCLOSURE OF THE INVENTION
Accordingly, an advantage of the present invention is in providing a system that enables a user to monitor host's access to various registers of a communication device.
Another advantage of the present invention is in providing a system that monitors access to registers in a communication device using hardware resources of the device.
These and other advantages of the invention are achieved at least in part by providing an access tracing system that comprises a trace register circuit having bits representing pre-selected registers. A decoder decodes an address signal from a host to supply the trace register circuit with a trace select signal indicating a register being accessed by the host, to assert a bit representing that register.
In accordance with one aspect of the invention, the decoder may also produce a register select signal for allowing the host to access the register.
In accordance with another aspect of the invention, the trace register circuit may comprise a read trace register for storing bits representing registers monitored for read access. The read trace register asserts a bit representing a selected register when the host performs read access to the selected register.
In accordance with a further aspect of the invention, the trace register circuit may also comprise a write trace register for storing bits representing registers monitored for write access. The write trace register asserts a bit representing a selected register when the host performs write access to the selected register.
In accordance with another aspect of the invention, a data communication system controlled by an external host and having data registers accessible by the host via a PCI bus may comprise read and write trace registers for storing bits identifying the data registers and a decoder responsive to an address signal from the host for controlling the read and write trace registers to assert a bit representing a register being accessed by the host.
The decoder may produce a trace select signal when the host performs read access to a monitored data register represented in the read trace register. In response to the trace select signal, the read trace register asserts a bit representing the monitored data register.
Further, the decoder may produce the trace select signal when the host performs write access to a monitored data register represented in the write trace register. In response to the trace select signal, the write trace register asserts a bit representing the monitored register.
In accordance with the method of the present invention, the following steps are carried out for tracing access to selected registers in a data processing device:
decoding address signals from a host to produce a trace select signal for a selected register to be accessed by the host, and
asserting a bit representing the selected register in a trace register circuit in response to the trace select signal.
The trace select signal initiates the assertion of a read trace bit in the trace register circuit when the host performs read access to the selected register. Also, the trace select signal initiates the assertion of a write trace bit in the trace register circuit when the host performs write access to the selected register.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
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Balmforth David
Haubursin Pierre F.
Tsai Din-I
Yu Ching
Advanced Micro Devices , Inc.
Iqbal Nadeem
McDermott & Will & Emery
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