Software programmable bus disable system

Details Software programmable bus disable system Software programmable bus disable system

1997-05-27

1999-07-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711150, 711151, 711152, 711158, 711213, G06F 1314

Patent

active

059241241

ABSTRACT:
A microcontroller, which is configured in a certain mode, may generate signals that can cause malfunctions of the microcontroller or of other devices. For example, a prefetch cycle at an internal memory boundary may attempt to access external memory via a port when the port is connected to an I/O device. The system of the invention gates such signals and thus prevents possible damage to the microcontroller or peripheral device. In a preferred embodiment, a software programmable register is provided with one location dedicated to storing a bit. When that register bit is set, it prevents certain signals and address/data from appearing at the port and thus possibly causing harm to the microcontroller or a peripheral device connected to the port.

REFERENCES:
patent: 4851989 (1989-07-01), Kagimasa et al.
patent: 5067077 (1991-11-01), Wakimoto
patent: 5247621 (1993-09-01), Gulick
patent: 5251304 (1993-10-01), Sibigtroth et al.
patent: 5452431 (1995-09-01), Bournas
patent: 5467461 (1995-11-01), Nasu et al.

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