Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-06-25
2008-12-23
Ellis, Kevin (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S135000, C718S108000
Reexamination Certificate
active
07469321
ABSTRACT:
A multiprocessor computer system has nodes which use processor state information to determine which coherent caches are required to examine a coherency transaction produced by a single originating processor's storage request. A node has dynamic coherency boundaries such that the hardware uses only a subset of the total processors for a single workload at any specific point in time and can optimize cache coherency as the supervisor software or firmware expands and contracts the number of processors used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a larger multiprocessor system. The node controllers use the mode bits to determine which nodes must receive any given transaction. Logical partitions are mapped to allowable physical processors. Cache coherence regions and caches are chosen for their physical proximity. A distinct cache coherency region can be hypervisor defined for each partition.
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Augspurger Lynn L.
Ellis Kevin
International Business Machines - Corporation
Rutz Jared I
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