Software power control of circuit modules in a shared and...

Details Software power control of circuit modules in a shared and... Software power control of circuit modules in a shared and...

2008-01-22

2008-01-22

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Inhibiting timing generator or component

C713S600000, C365S202000

Reexamination Certificate

active

07321980

ABSTRACT:
A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bit indicates the power-up state and a reset mode if the bit indicates a power-down state. Return to normal mode is delayed a predetermined time after the said bit of indicates the power-up state to ensure clean power up. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the corresponding bit indicates the power-down state.

REFERENCES:
patent: 4513378 (1985-04-01), Antkowiak
patent: 6298394 (2001-10-01), Edwards et al.
patent: 2003/0005278 (2003-01-01), Deng et al.
patent: 2004/0250147 (2004-12-01), Chang
patent: 2006/0179329 (2006-08-01), Terechko et al.

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