Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-14
2000-05-02
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711130, 711128, G06F 1208
Patent
active
060584564
ABSTRACT:
A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage of the cache by each value class and selecting a desired ratio of cache usage by the classes from among a plurality of available ratios, and cache blocks within the cache are evicted using a cache-replacement mechanism which restricts replacement of an evicted cache to a particular one of the classes of values (instruction or data) based on the desired ratio of cache usage. A multi-bit facility may be provided to indicate how to confine a selected victim to certain cache blocks, and the program instructions select the desired ratio of cache usage by setting the multi-bit facility. The cache-replacement mechanism can be a modified least recently used replacement mechanism. Different instruction/data ratios thereby may be provided, such as 1:1, 1:2, and 2:1.
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Arimilli Ravi Kumar
Clark Leo James
Dodson John Steven
Lewis Jerry Don
Bataille Pierre-Michel
Cabeca John W.
Dillon Andrew J.
Henkler Richard A.
International Business Machines - Corporation
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