Software direct memory access

Details Software direct memory access Software direct memory access

1999-12-15

2003-12-23

Perveen, Rehana (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S024000, C710S048000, C710S052000

Reexamination Certificate

active

06668287

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for allowing input/output devices to directly access memory.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (called “code morphing software”) to execute application programs designed for a processor different than the morph host processor at a rate which cannot be attained by the processor for which the programs were designed (the target processor). The morph host processor executes the code morphing software to translate the application programs into morph host processor instructions which accomplish the purpose of the original target software. As the target instructions are translated, they are both executed and stored in a translation buffer where they may be accessed without further translation. Although the initial translation and execution of a program is slow, once translated, many of the steps normally required to execute a program in hardware are eliminated.
In order to be able to execute programs designed for other processors at a rapid rate, the morph host processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer which resides between the host processor and the translation buffer. A second enhancement is a set of host registers which store the state of the target machine at the beginning of any sequence of target instructions being translated. Sequences of target instructions spanning known states of the target processor are translated into morph host instructions and placed in the translation buffer awaiting execution. If the translated instructions execute without raising an exception, the target state at the beginning of the sequence of instructions is updated to the target state at the point at which the sequence completed.
If an exception occurs during the execution of the sequence of host instructions which have been translated, the processing stops; and the entire operation may be returned to the beginning of the sequence of target instructions at which known state of the target machine exists. This allows very rapid and accurate handling of exceptions while dynamically translating and executing instructions, a result which had never been accomplished by the prior art.
Another hardware enhancement that the new microprocessor includes is circuitry for aliasing memory data that is frequently utilized during execution of a series of instructions in execution unit registers. Aliasing (or copying memory contents to a register) allows very rapid access of memory for data which is used frequently during a series of operations.
Although the new microprocessor includes a number of hardware features which allow the code morphing software and the morph host to cooperate with one another to carry out the functions of a typical microprocessor, the new microprocessor does not include most of the hardware features utilized by a conventional microprocessor. The new processor is described in detail in U.S. Pat. No. 5,926,832, entitled
Method and Apparatus for Aliasing Memory Data in an Advanced Microprocessor
, Wing et al, issued Jul. 20, 1999, and assigned to the assignee of the present application.
One of the hardware features of a typical microprocessor which is not included is hardware by which direct access of memory by input/output (I/O) devices may be accomplished. Direct memory access (DMA) is especially desirable because it allows the use of master I/O devices which may themselves control operations on the I/O bus such as the storage in memory of data being transferred to the computer.
However, the hardware required to provide direct memory access is quite complicated and significantly increases the circuitry of a processor. Such circuitry typically includes not only circuitry for accomplishing the direct access of memory but circuitry which checks the ordering of operations and assures the maintenance of consistency for data stored in various caches of a microprocessor in order to allow the use of DMA circuitry. Circuitry for maintaining consistency, especially, would need to be greatly enhanced for hardware DMA to be utilized in the new microprocessor because of the large increase in functions that have cache-like aspects in the new microprocessor. For example, data held in the gated store buffer before being stored in memory and memory data aliased in execution unit registers to speed memory access operations must be consistent with memory data. Moreover, translated instructions stored in the translation buffer that are affected by direct access of target memory must be cognizant that the memory upon which they depend may have changed invalidating the translation.
It is desirable to provide circuitry and software for allowing direct memory access in a computer utilizing the new microprocessor.
SUMMARY OF THE INVENTION
The present invention is realized by apparatus and a method for generating an interrupt when a direct memory access by an I/O device is desired, suspending the operation of the microprocessor in response to the interrupt, placing state of the morph host to a last known correct state in response to the interrupt, determining the memory operation commanded by the I/O device, and utilizing the microprocessor to execute the memory operation commanded by the I/O device.


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