Electrical computers and digital processing systems: virtual mac – Task management or control
Reexamination Certificate
2008-03-11
2008-03-11
An, Meng-Al T. (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
C712S228000, C712S229000, C711S117000
Reexamination Certificate
active
07343602
ABSTRACT:
A processor capable of running multiple threads runs a program in one thread (called the “main” thread) and at least a portion of the same program in another thread (called the “pre-execution” thread). The program in the main thread includes instructions that cause the processor to start and stop pre-execution threads and direct the processor as to which part of the program is to be run through the pre-execution threads. Preferably, such instructions cause the pre-execution thread to run ahead of the main thread in program order. In that way, any cache miss conditions that are encountered by the pre-execution thread are resolved before the main thread requires that same data. Therefore, the main thread should encounter few or no cache miss conditions.
REFERENCES:
patent: 5138708 (1992-08-01), Vosbury
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5261097 (1993-11-01), Saxon
patent: 5339415 (1994-08-01), Strout et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5781776 (1998-07-01), Johnston et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815727 (1998-09-01), Motomura
patent: 5904732 (1999-05-01), Greenley et al.
patent: 5933860 (1999-08-01), Emer et al.
patent: 5978838 (1999-11-01), Mohamed et al.
patent: 6032245 (2000-02-01), Georgiou et al.
patent: 6199117 (2001-03-01), Cox et al.
patent: 6219782 (2001-04-01), Khan et al.
patent: 6353881 (2002-03-01), Chaudhry et al.
patent: 6457063 (2002-09-01), Chintalapati et al.
patent: 6757811 (2004-06-01), Mukherjee
patent: 6928645 (2005-08-01), Wang et al.
Rotenberg, Eric, “ArSMT: A Microarchitecutal Approcach to Fault Tolerane in Microprocessor”, 29th Int'l Symp on Fault-Tolerant Computing, Jun. 1999, 8 pages.
Akkary et al., “A Dynamic Multithreading Processor”, 1998, IEEE, pp. 1-11.
Marcuello et al., “Exploiting Speculative Thread-Level Parallelism on a SMT Processor”, 1999, AC.UPC.ES, pp. 1-12.
M. Franklin, “Incorporating Fault Tolerance in Superscalar Processors,” Proceedings of High Performance Computing, Dec. 1996 (pp. 301-306).
A. Mahmood et al., “Concurrent Error Detection Using Watchdog Processors—A Survey,” IEEE Trans. on Computers, vol. 37, No. 2, Feb. 1988 (pp. 160-174).
J. H. Patel et al., “Concurrent Error Detection In ALU's by Recomputing With Shifted Operands,” IEEE Trans. on Computers, vol. 31, No. 7, Jul. 1982 (pp. 589-595).
D. A. Reynolds et al., “Fault Detection Capabilities Of Alternating Logic,” IEEE Trans. on Computers, vol. 27, No. 12, Dec. 1978 (pp. 1093-1098).
E. Rotenberg et al., “Trace Cache: A Low Latency Approach To High Bandwidth Instruction Fetching,” Proceedings of the 29th Annual International Symposium on Microarchitecture, Dec. 1996 (pp. 24-34).
E. Rotenberg et al., “Trace Processors,” 30th Annual International Symposium on Microarchitecture (Micro-30), Dec. 1997(pp. 138-148).
T. J. Slegel et al., “IBM's S/390 G5 Microprocessor Design,” IEEE Micro, pp. 12-23, Mar./Apr. 1999 (pp. 12-23).
J. E. Smith et al., “Implementing Precise Interrupts In Pipelined Processors,” IEEE Trans. on Computers, vol. 37, No. 5, May 1988 (pp. 562-573).
G. S. Sohi et al., “A Study Of Time-Redundant Fault Tolerance Techniques For High-Performance Pipelined Computers,” Digest of Papers, 19th International Symposium in Fault-Tolerant Computing, 1989 (pp. 436-443).
G. S. Sohi et al., “Instruction Issue Logic For High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers,” IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990 (pp. 349-359).
D. M. Tullsen, et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proceedings of the 22nd Annual International Symposium on Computer Architecture, Italy, Jun. 1995 (12 pp.).
S. K. Reinhardt et al., “Transient Fault Detection Via Simultaneous Multithreading,” undated (12 pp.).
L. Spainhower et al., “IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective,” IBM J. Res. Develop. vol. 43, No. 5/6, Sep./Nov. 1999 (pp. 863-873).
M. Franklin, “A Study Of Time Redundant Fault Tolerance Techniques For Superscalar Processors,” undated (9 pp.).
Emer Joel S.
Luk Chi-Keung
An Meng-Al T.
Hewlett--Packard Development Company, L.P.
To Jennifer N.
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