Software controlled hard reset of mastering IPS

Details Software controlled hard reset of mastering IPS Software controlled hard reset of mastering IPS

2008-01-01

2008-01-01

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

C710S008000, C713S001000

Reexamination Certificate

active

07315905

ABSTRACT:
A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.

REFERENCES:
patent: 6073253 (2000-06-01), Nordstrom et al.
patent: 6633938 (2003-10-01), Rowlands et al.

Affiliated with

Also associated with

Rating

Software controlled hard reset of mastering IPS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Software controlled hard reset of mastering IPS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Software controlled hard reset of mastering IPS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2744600