Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-10
2006-10-10
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07120748
ABSTRACT:
The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.
REFERENCES:
patent: 5594886 (1997-01-01), Smith et al.
patent: 5708789 (1998-01-01), McClure
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5974507 (1999-10-01), Arimilli et al.
patent: 6425058 (2002-07-01), Arimilli et al.
patent: 6430656 (2002-08-01), Arimilli et al.
patent: 6430667 (2002-08-01), Loen
patent: 6826652 (2004-11-01), Chauvel et al.
patent: 2003/0159003 (2003-08-01), Gaskins et al.
patent: 2004/0143708 (2004-07-01), Caprioli
Demaine, Erik D. “Cache-Oblivious Algorithms and Data Structures”, Lecture Notes in Computer Science, BRICS, University of Aarhus, Denmark, Jun. 27-Jul. 1, 2002, pp. 1-29.
Al-Zoubi et al. “Performance Evaluation of Cache Replacement Policies for the SPEC2000 Benchmark Suite”. 2004. Proceedings of the 42ndAnnual ACM Southeast Regional Conference, ACM, pp. 267-272.
Day Michael Norman
Hofstee Harm Peter
Johns Charles Roy
Kahle James Allan
Shippy David
Carr LLP
Doan Duc T
Gerhardt Diana R.
LandOfFree
Software-controlled cache set management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Software-controlled cache set management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Software-controlled cache set management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3676014