Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-08-17
2004-01-20
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S134000, C711S135000, C711S138000, C711S139000, C711S133000
Reexamination Certificate
active
06681297
ABSTRACT:
This application claims priority to European Application Serial No. 00402331.3, filed Aug. 21, 2000 European Application Serial No. 00403538.2, filed Dec. 15, 2000 and to European Application Serial No. 01401532.5, filed Jun. 13, 2001. U.S. patent application Ser. No. 09/932,651 is incorporated herein by reference.
1. Field of the Invention
This invention generally relates to microprocessors, and more specifically to improvements in cache memory access circuits, systems, and methods of making.
2. Background
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a cache with an array of data lines with an associated array of tags. Data is loaded into various of lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, a qualifier value is stored in a qualifier field in the tag. The qualifier value specifies a usage characteristic of data stored in an associated data line of the cache. A miss rate is determined for memory requests in which a requested data value for a selected monitored-qualifier value is not valid within the cache. A threshold value for the miss rate is selected and an aspect of the digital system is reconfigured if the miss rate exceeds the threshold value. One manner of reconfiguration is flushing a set of entries which have a selected qualifier value.
Another manner of reconfiguration is remapping a selected program portion to operate in a different address range.
Another manner of reconfiguration is locking a portion of the data entries within the cache or within a RAM Set of a SmartCache.
Another manner of reconfiguration is defining ranges of addresses corresponding to a selected program task as uncacheable.
In another embodiment, a digital system is provided with a cache that has a data array with a set of lines for holding data and a tag array having a set of lines for holding a set of tags. Each line of the tag array is associated with a particular line of the data array and each line of the tag array contains an address field and a qualifier field. A miss counter counts each cache memory request miss corresponding to a monitored-qualifier value, such as a task-ID, and a monitoring task determines a miss rate for memory requests. If a selected miss rate threshold value is exceeded, the digital system is reconfigured in order to reduce the miss rate. The cache is reconfigured in response to an operation command, such that each tag in the set of tags that contains a specified qualifier value is modified in accordance with the operation command.
REFERENCES:
patent: 5761715 (1998-06-01), Takahashi
patent: 5978888 (1999-11-01), Arimilli et al.
IBM Technical Disclosure Bulletin, IBM Corp., NY, US;Scheme for Producing Miss-Rate as a Function of Cache Size by Means of Traces Produced by Observing Misses From a Cache of Fixed Size,vol. 33, No. 11, Apr. 1, 1991, pp. 36-39.
Texas Instruments Incorporated, S/N: 09/187,118, filed Nov. 5, 1998,Computer Circuits, Systems, and Methods Using Partial Cache Cleaning.
Texas Instruments Incorporated, S/N: 09/447,194, filed Nov. 22, 1999,Optimized Hardware Cleaning Function for VIVT Data Cache.
Chauvel Gerard
D'Inverno Dominique
Lasserre Serge
Brady III W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Verbrugge Kevin
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