Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-11-29
2005-11-29
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S117000, C710S124000, C710S045000, C710S046000, C710S044000, C711S151000, C713S001000
Reexamination Certificate
active
06970986
ABSTRACT:
An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.
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Adaptec, Inc.
Bataille Pierre-Michel
Martine & Penilla & Gencarella LLP
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