Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2005-10-12
2009-11-17
Patel, Niketa I (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S005000, C710S048000, C709S212000, C711S112000
Reexamination Certificate
active
07620747
ABSTRACT:
Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.
REFERENCES:
patent: 5428779 (1995-06-01), Allegrucci et al.
patent: 5761454 (1998-06-01), Adusumilli et al.
patent: 2004/0158669 (2004-08-01), Weng et al.
Huffman et al, “Serial ATA Native Command Queuing”, Joint Whitepater By : Intel Corporation and Seagate Technology, Jul. 2003.
Chen Xing Cindy
Overby Mark A.
Huson Zachary K
NVIDIA Corporation
Patel Niketa I
Patterson & Sheridan LLP
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