Electronic digital logic circuitry – Tri-state
Patent
1994-05-19
1996-02-06
Westin, Edward P.
Electronic digital logic circuitry
Tri-state
326 21, 326 83, H03K 1900, H03K 1716
Patent
active
054898587
ABSTRACT:
Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
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Erickson Charles R.
Pierce Kerry M.
Roseen Richard
Westin Edward P.
Xilinx , Inc.
Young Edel M.
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