Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-04-09
2002-12-10
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06493266
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to memory systems and in particular, to flash memory systems and methods wherein a new reference cell structure, and the application of unique reference voltages during soft program and soft program verify operations, eliminates previous problems of trimming a reference cell to a low threshold voltage, and tightens the erased core cell threshold voltage distribution, which also facilitates faster programming times.
BACKGROUND OF THE INVENTION
Flash memory is a type of electronic memory media which can be rewritten and hold its data without power. Flash memory devices generally have life spans from 100K to 1 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell, for example, as illustrated in prior art
FIG. 1
a
, and designated at reference numeral
10
. In such single bit memory architectures, each cell
10
typically includes a metal oxide semiconductor (MOS) transistor structure having a source
12
, a drain
14
, and a channel
16
in a substrate or P-well
18
, as well as a stacked gate structure
20
overlying the channel
16
. The stacked gate
20
may further include a thin gate dielectric layer
22
(sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate
20
also includes a polysilicon floating gate
24
overlying the tunnel oxide
22
and an interpoly dielectric layer
26
overlying the floating gate. The interpoly dielectric layer
26
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
28
overlies the interpoly dielectric layer
26
.
The control gate
28
is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions
14
of the cells are connected together by a conductive bit line. The channel
16
of the cell conducts current between the source
12
and the drain
14
in accordance with an electric field developed in the channel
16
by the stacked gate structure
20
. In the NOR configuration, each drain terminal
14
of the transistors within a single column is connected to the same bit line. In addition, each flash cell associated with a given bit line has its stacked gate terminal
28
coupled to a different word line, while all the flash cells in the array have their source terminals
12
coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry (not shown) for programming (writing), reading or erasing functions.
Such a conventional single bit stacked gate flash memory cell
10
is programmed by applying a relatively high voltage to the control gate
28
and connecting the source
12
to ground and the drain
14
to a predetermined potential above the source. A resulting high electric field across the tunnel oxide
22
leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region
16
tunnel through the gate or tunnel oxide
22
into the floating gate
24
and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric
26
and the tunnel oxide
22
. As a result of the trapped electrons, the threshold voltage of the cell
10
increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a conventional single bit stacked gate flash memory cell
10
, a relatively high voltage is applied to the source
12
, and the control gate
28
is held at a negative potential, while the drain
14
is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
22
between the floating gate
24
and the source
12
. The electrons that are trapped in the floating gate
24
flow toward and cluster at the portion of the floating gate overlying the source region
12
and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide
22
. As the electrons are removed from the floating gate
24
, the cell
10
is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
After erasure, some cells may have been over erased, producing an excessively low threshold voltage and corresponding high drain current leakage which may cause problems with later read, program verify, or even erase operations. The process of soft programming has typically been adopted as a means to correct the over erased cells. Usually this process involves applying one or more program pulses to the over erased cells. The soft program process raises (or corrects) the low threshold voltages of the identified cells, to effectively narrow the distribution of erased cell threshold voltages across a flash memory array.
Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell.
FIG. 1
b
illustrates an exemplary prior art dual bit memory cell
50
. The memory cell
50
comprises a silicon dioxide layer
52
, a P-type substrate
54
has buried N+ source
56
and N+ drain
58
regions. The silicon dioxide
52
is sandwiched between two layers of silicon nitride
60
, and
62
. Alternatively, the layer
52
may comprise buried polysilicon islands or any other form of charge trapping layer.
Overlying the nitride layer
60
is a polysilicon gate
64
. This gate
64
is doped with an N-type impurity (e.g., phosphorus). The memory cell
50
is capable of storing two data bits, a left bit represented by the dashed circle A and a right bit represented by the dashed circle B. The dual bit memory cell
50
is generally symmetrical, thus the drain
58
and the source
56
are interchangeable. Thus, the left junction
56
may serve as the source terminal and the right junction
58
as the drain terminal with respect to the right bit B. Likewise, the right junction
58
may serve as the source terminal and the left junction
56
as the drain terminal for the left bit A.
After erasure of a dual bit cell, the conventional soft programming, and soft program verification methods employed with single bit stacked gate architectures may be applied in certain circumstances to such dual bit devices, but are problematic at best because the end of the erase distribution V
T
's are not close to zero, but are at 0.7 volts. Therefore, there is a need for new and improved soft programming, and soft program verification methods and systems, which ensure proper control of the erased cell threshold voltage distribution of data bits in a dual bit memory architecture, and which account for the structural characteristics thereof.
SUMMARY OF THE INVENTION
A system and methodology are provided which overcome or minimize t
Hamilton Darlene G.
Kurihara Kazuhiro
Le Binh Q.
Yachareni Santosh K.
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Tran M.
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