Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2009-04-27
2010-06-22
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S040000
Reexamination Certificate
active
07741865
ABSTRACT:
In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.
REFERENCES:
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5870327 (1999-02-01), Gitlin et al.
patent: 5886392 (1999-03-01), Schuegraf
patent: 6128218 (2000-10-01), You et al.
patent: 6208549 (2001-03-01), Rao et al.
patent: 6237124 (2001-05-01), Plants
patent: 6625080 (2003-09-01), Casper et al.
patent: 7023744 (2006-04-01), Shimanek et al.
patent: 7036059 (2006-04-01), Carmichael et al.
patent: 7064574 (2006-06-01), Voogel et al.
patent: 7200235 (2007-04-01), Trimberger
patent: 2004/0165418 (2004-08-01), Lesea
patent: 2004/0227551 (2004-11-01), Gardner
patent: 2004/0257108 (2004-12-01), Carlson et al.
patent: 2007/0103185 (2007-05-01), Friedman
patent: 2007/0111403 (2007-05-01), Jiang et al.
Sharpe-Geisler Brad
Singh Satwant
Cho James H.
Haynes and Boone LLP
Lattice Semiconductor Corporation
Tabler Matthew C
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