Soft error resistant semiconductor memory device

Details Soft error resistant semiconductor memory device Soft error resistant semiconductor memory device

2003-09-24

2004-11-09

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S066000, C257S067000, C257S379000, C257S380000, C257S381000, C257S758000, C257S904000

Reexamination Certificate

active

06815839

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device having a memory cell of SRAM (static random access memory) type. More particularly, this invention relates to a semiconductor memory device improved in resistance to soft error.
BACKGROUND OF THE INVENTION
As the electronic appliances are becoming lighter, thinner and shorter recently, there is also an increasing demand for realizing the functions of these appliances at high speed. In such electronic appliances, the microcomputer is indispensable, and memories of large capacity and high speed are needed in the microcomputer. At the same time, along with the rapid spread and sophistication of personal computers, cache memories of larger capacity are required for realizing processing at higher speed.
As the RAM, generally, the DRAM (dynamic RAM) and SRAM have been used, and especially the SRAM is used where high speed processing is demanded, such as the cache memory. According to its memory cell structure, the SRAM is available in the high resistance load type composed of four transistors and two high resistance elements, and the CMOS type composed of six transistors. In particular, the CMOS type SRAM is high in reliability because the leak current while holding data is very small, and it is in the mainstream at the present.
FIG. 18
is an equivalent circuit diagram of memory cell of a conventional CMOS type SRAM. In
FIG. 18
, a PMOS transistor P
1
(load transistor) and an NMOS transistor N
1
(drive transistor) compose a first CMOS inverter, and a PMOS transistor P
2
(load transistor) and an NMOS transistor N
2
(drive transistor) compose a second CMOS inverter, and input and output terminals are connected complementarily between the first and second CMOS inverters.
That is, a flip-flop circuit is composed of these MOS transistors P
1
, P
2
, N
1
, and N
2
, in FIG.
18
and the logic state can be written and read at a memory node NA which is the output point of the first CMOS inverter and also the input point of the second CMOS inverter, and a memory node. NB which is the output point of the second CMOS inverter and also the input point of the first CMOS inverter.
Further, NMOS transistors N
3
and N
4
function as access transistors, and the NMOS transistor N
3
has its gate connected to a word line WL, the source connected to the memory node NA, and the drain connected to a positive phase bit line BL. The NMOS transistor N
4
has its gate connected to the word line WL, the source connected to the memory node NB, and the drain connected to a negative phase bit line BLB.
That is, by selection of word line WL, positive phase bit line BL, and negative phase bit line BLB, the memory value stored in the memory node NA or NB can be read out.
FIG. 19
is a layout diagram of SRAM memory cell corresponding to the equivalent circuit shown in FIG.
18
. As shown in
FIG. 19
, one SRAM memory cell is formed on an N-type well region NW and a P-type well region PW formed on a semiconductor substrate. Further, PMOS transistors P
1
and P
2
shown in the equivalent circuit are formed in the same N-well region NW, and NMOS transistors N
1
to N
4
are formed in the same P-well region PW.
The PMOS transistor P
1
comprises a source region and a drain region, which are P+ diffusion regions FL
100
and FL
110
formed by injection of P-type impurity respectively, and a gate region formed between the P+ diffusion regions FL
100
and FL
110
and a polysilicon wiring layer PL
110
. Similarly, the PMOS transistor P
2
comprises a source region and a drain region, which are P+ diffusion regions FL
100
and FL
120
formed by injection of P-type impurity respectively, and a gate region formed between the P+ diffusion regions FL
100
and FL
120
and a polysilicon wiring layer PL
120
. That is, the PMOS transistors P
1
and P
2
share the P+ diffusion region FL
100
as the source region.
The NMOS transistor N
1
comprises a source region and ga drain region, which are N+ diffusion regions FL
200
and FL
210
formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL
200
and FL
210
and a polysilicon wiring layer PL
110
. Similarly, the NMOS transistor N
2
comprises a source region and a drain region, which are N+ diffusion regions FL
200
and FL
220
formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL
200
and FL
220
and a polysilicon wiring layer PL
120
. That is, the NMOS transistors N
1
and N
2
share the N+ diffusion region FL
200
as the source region.
The NMOS transistor N
3
comprises a source region and a drain region, which are N+ diffusion regions FL
230
and FL
210
formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL
230
and FL
210
and a polysilicon wiring layer PL
140
. That is, the NMOS transistors N
1
and N
3
share the N+ diffusion region FL
210
as the source region.
The NMOS transistor N
4
comprises a source region and a drain region, which are N+ diffusion regions FL
240
and FL
220
formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL
240
and FL
220
and a polysilicon wiring layer PL
130
. That is, the NMOS transistors N
2
and N
4
share the N+ diffusion region FL
220
as the source region.
The polysilicon wiring layer PL
110
functions also as the wiring for connecting between the gate regions of the PMOS transistor P
1
and NMOS transistor N
1
, and the polysilicon wiring layer PL
120
also functions as the wiring for connecting between the gate regions of the PMOS transistor P
2
and NMOS transistor N
2
.
At least one or more contact holes are formed each in the P+ diffusion regions FL
100
, FL
110
and FL
120
, N+ diffusion regions FL
200
, FL
210
, FL
220
, FL
230
and FL
240
, and polysilicon wiring layers PL
110
, PL
120
, PL
130
and PL
140
. In order to realize the connection and composition of the equivalent circuit shown in
FIG. 18
, these contact holes are mutually connected through metal or other upper wiring layers.
Various structures may be considered for upper wiring layers for connecting the contact holes, but for the ease of understanding, in
FIG. 19
, the connecting wiring of contact holes is indicated schematically by thick solid lines. According to
FIG. 19
, the P+ diffusion region FL
110
, N+ diffusion region FL
210
, and polysilicon wiring layer PL
120
are electrically connected through the upper wiring layer to compose the memory node NA, and the P+ diffusion region FL
120
, N+ diffusion region FL
220
, and polysilicon wiring layer PL
110
are electrically connected through the upper wiring layer to compose the memory node NB.
The P+ diffusion region FL
100
is connected to a VDD line, which is a power source line, through the contact hole and upper wiring layer, and the N+ diffusion region FL
200
is connected to a GND line, which is a grounding line, through the contact hole and upper wiring layer. The N+ diffusion regions FL
230
and FL
240
are electrically connected to the positive phase bit line BL and negative phase bit line BLB, respectively, through the contact hole and upper wiring layer. Further, the polysilicon wiring layers PL
130
and PL
140
are electrically connected to the word line WL through the contact hole and upper wiring layer.
A sectional structure of the conventional SRAM memory cell is explained.
FIG. 20
is a sectional view along line A—A′ in the conventional SRAM memory cell layout in FIG.
19
. In order to form PMOS transistors P
1
and P
2
, first, the P+ diffusion regions FL
100
, FL
110
, and FL
120
partitioned by an element separation region
10
are formed on an N-well region NW. After laminating a thin insulating film
21
between the P+ diffusion regions, by laminating polysilicon wiring layers PL
110
and PL
120
thereon, a gate electrode electrical

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