Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-12-29
2002-04-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000, C326S021000
Reexamination Certificate
active
06366132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to circuits and, more particularly, to soft error resistant circuits, such as latches and dynamic circuits.
2. Background Art
Integrated circuit technology design has scaled over time. In particular, operating voltage and transistor device dimensions have become smaller and the chips are operating at higher frequencies. Hence the integrated circuits are becoming more susceptible to external interference. Cosmic rays have caused soft errors in memories and storage elements in the chips used at high altitudes by the aerospace community. A soft error is a change in the voltage state of a node in a circuit due to cosmic rays. Cosmic rays are increasingly likely to cause soft errors in integrated chips at ground levels because of the scaling of dimensions and voltage. The storage elements in a datapath such as in static latches and dynamic gates are becoming susceptible to soft errors and there is concern for an associated soft error rate (SER). Additional complexity arises from the lack of error correction in datapath.
Both neutrons and alpha particles can cause soft errors. Neutrons may cause hole-electron pairs in the substrate and also in wells close to the surface of the integrated circuit. An alpha particle may also cause hole-electron pairs to be created in the substrate, but it is believed that the alpha particles typically travel deeper into the integrated circuit so as to pass through wells.
As an example,
FIG. 1
illustrates a schematic cross-sectional view of a portion of an integrated circuit
10
having an n-channel metal oxide semiconductor field effect transistor (NMOSFET)
14
and p-channel metal oxide semiconductor field effect transistor (PMOSFET)
16
. In the example, the drain diffusions D of NMOSFET
14
and PMOSFET
16
are connected at a node N
1
and the source diffusions S are respectively connected to a ground voltage (sometimes called Vss) and power supply voltage (sometimes called Vdd or Vcc). Assume the gates G of NMOSFET
14
and PMOSFET
16
are connected. Assume hole-electron pairs + and − are created in the p-substrate and also in the n-well of integrated circuit
10
.
The electrons (−) in the n-well are attracted to Vdd and the holes (+) in the p-substrate are attracted to Vss. If PMOSFET
16
is on and NMOSFET
14
is off, the drains are pulled high (Vcc). In that case, the electrons (−) in the p-substrate are attracted to drain diffusion D of NMOSFET
14
. If there are enough electrons attracted to drain diffusion D, the voltage state of node N
1
might change from high to low. Likewise, if PMOSFET
16
is off and NMOSFET
14
is on, the drains are pulled low (Vss). In that case, the holes (+) in the n-well are attracted to drain diffusion D of PMOSFET
16
. If there are enough holes attracted to drain diffusion D, the voltage state of node N
1
might change from low to high. With a closed loop system, the change in state may be permanent.
There is a need for soft error resistant techniques for datapath and control circuits that have a relatively small effect on performance.
SUMMARY
In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node.
In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes.
In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.
Additional embodiments are described and claimed.
REFERENCES:
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patent: 5903180 (1999-05-01), Hsia et al.
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patent: 6107852 (2000-08-01), Durham et al.
T. Calin et al. “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE Transactions on Nuclear Science, vol. 43, No. 6, Dec. 1996, pp. 2874-2878.
Karnik Tanay
Krishnamurthy Ram K.
Aldous Alan K.
Intel Corporation
Le Don Phu
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