Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1998-01-21
2000-04-04
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326112, 326121, H03K 19096, H03K 19094, H03K 1920
Patent
active
060466065
ABSTRACT:
A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
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Chu Sam Gat-Shang
Kodali Visweswara Rao
Lee Michael Ju Hyeok
Chang Daniel
England Anthony V.S.
International Business Machines - Corporation
Tokar Michael
Wilder Robert V.
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