Soft error detection in high speed microprocessors

Details Soft error detection in high speed microprocessors Soft error detection in high speed microprocessors

2000-08-03

2004-08-31

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S042000, C714S049000, C714S054000, C714S819000, C712S221000

Reexamination Certificate

active

06785847

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to soft errors in high speed microprocessors.
BACKGROUND OF THE INVENTION
Soft errors due to alpha particle radiation are commonplace in integrated circuits, particularly in latches and memory elements. This source is not limited to cosmic rays. On-chip solder bumps produce alpha particles themselves, as they contain lead. Hence, storage nodes are subjected to more probable single event upsets (soft errors) due to alpha particles than in the past. This may cause the storage node to flip and lose its contents.
A block diagram of a GPR (general purpose register)
10
is illustrated in FIG.
1
. Signals rd
0
_data<
0
:
63
> through rd
3
_data<
0
:
63
> are the 64 bit read data outputs of port
0
through port
3
, respectively. Corresponding read addresses are rd
0
_addr<
0
:
6
> through rd
3
_addr<
0
:
6
>; they support an address range from 0 to 127. In this example, only entries corresponding to addresses
0
to
79
exist; addresses
80
through
127
do not exist and cannot be read or written. Signals wr
0
_data<
0
:
63
> through wr
4
_data<
0
:
63
> indicate 64 bit write data inputs for ports
0
through
4
, respectively. Similar to the read ports, wr
0
_addr<
0
:
6
> through wr
4
_addr<
0
:
6
> represent 7-bit wide addressing for corresponding write ports
0
through
4
.
One method for detecting soft errors is to add a parity bit to each of the GPR entries.
FIG. 2
illustrates a GPR
10
showing the bit positions of the entries
12
along with a parity bit
14
. With the GPR
10
having 4 read and 5 write ports, nine 64-way exclusive OR (XOR) circuits are required for parity generation. Furthermore, the parity generation may not be accomplished in the same clock cycle and would have to be delayed by one clock cycle. These constraints are often not acceptable for some systems to detect soft errors.
Now, taking as an example, a Power 4 superscalar microprocessor chip from IBM Corporation, Armonk, N.Y., where there are two Fixed Point Unit (FXU) pipelines, a GPR must provide five write and eight read ports. Arrays and register files are commonly replicated in high frequency, superscalar microprocessor design to satisfy the required number of read ports without affecting cycle time. Thus, to avoid the complexity of an eight read port memory cell, it is commonplace that each FXU pipeline has its own four read and five write port GPR file.
FIG. 3
illustrates FXU pipelines
16
and
18
, each having a four read and five write port GPR file
20
,
22
. Both GPRs
20
and
22
must hold identical data for the superscalar design to satisfy the architecture and the programming model. In practice, this copying of data is achieved with a delay of one clock cycle, and the basic mechanism for the transfer of data from FXU pipeline
0
16
to FXU pipeline
1
18
and FXU pipeline
1
18
to FXU pipeline
0
16
is illustrated in FIG.
3
. As shown in
FIG. 3
, if an adder
24
in FXU pipeline
0
16
writes to write port
0
of the GPR
20
in FXU pipeline
0
16
, the write data is transmitted to FXU pipeline
1
18
through latch
26
(LATCH_
0
_TO_
1
<
0
:
63
>, indicating one latch for each data bit). The latch
26
introduces one clock cycle delay for this operation. In this example, master slave latches are deployed. These are clocked with non-overlapping LSSD (Level sensitive scan design) clocks, cclk and bclk. It should be noted that any other clocking scheme would work as well. A similar operation may also be observed in
FIG. 3
, where the multiplier
28
in FXU pipeline
1
18
writes to write port
4
and then sends data to FXU pipeline
0
16
through latch
30
(LATCH_
1
_TO_
0
<
0
:
63
>). This connection of execution engine (adder
24
, multiplier
28
) to the register file is merely representative for the connections within any superscalar processor, and the details will vary across implementations.
Taking advantage of the fact that the GPRs must contain identical data by one clock cycle delayed, a fifth read port
31
may be added to each register file
20
′ and
22
′, as shown in FIG.
4
. The data outputs of the fifth read ports
31
may be fed to a comparator
32
, as depicted in
FIG. 4
, in order to determine data integrity. The comparator
32
issues a machine_check signal if a difference in the content of the two GPRs
20
′ and
22
′ exists. A fifth read port, however, increases the design complexity, as well as the cell size. In addition, a 64-bit comparator must be added.
Accordingly, what is needed is a mechanism that allows detection of soft errors in replicated arrays and register files. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides aspects for soft error detection for a superscalar microprocessor. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.
Through the present invention, soft error detection occurs in a manner that overcomes deficiencies with prior art approaches. The present invention provides soft error detection efficiently by taking advantage of an existing data transfer mechanism and a 64-bit comparator already in the ALU of FXU pipelines. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.


REFERENCES:
patent: 5125094 (1992-06-01), Kyuma
patent: 5638526 (1997-06-01), Nakada
patent: 5764943 (1998-06-01), Wechsler
patent: 5790826 (1998-08-01), Thusoo et al.
patent: 6263424 (2001-07-01), Tran et al.
patent: 6658621 (2003-12-01), Jamil et al.
patent: 2001/0034854 (2001-10-01), Mukherjee
1999 IEEE International Solid-State Circuits Conference, MP 5.2 600MHz G5 S/390 Microprocessor, 2 pages.

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