Electronic digital logic circuitry – Reliability
Reexamination Certificate
2011-07-12
2011-07-12
Barnie, Rexford N (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S012000, C326S095000, C327S208000, C327S218000
Reexamination Certificate
active
07977965
ABSTRACT:
A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking. Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
REFERENCES:
patent: 5881078 (1999-03-01), Hanawa
patent: 6624677 (2003-09-01), Wissel
patent: 6668341 (2003-12-01), Krauch
patent: 6718494 (2004-04-01), Jamil
patent: 6975238 (2005-12-01), Schneider
patent: 7482831 (2009-01-01), Chakraborty
patent: 7506230 (2009-03-01), Chu
patent: 7546519 (2009-06-01), Agarwal
patent: 7562273 (2009-07-01), Chu
patent: 2006/0184852 (2006-08-01), Chu
patent: 2007-052596 (2007-03-01), None
patent: WO2005041410 (2005-05-01), None
“Variation-Tolerant Hierarchical Voltage Monitoring Circuit for Soft Error Detection”, Narsale, et al. http://www.ece.rochester.edu/˜mihuang/PAPERS/isqed09.pdf.
Das et al., “A Self-Tuning DVS Processor Using Delay-Error Detection and Correction” IEEE JSSC, vol. 41, No. 4, pp. 792-804, (2006).
Das et al., “RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance” IEEE JSSC, vol. 44, No. 1, pp. 32-48, (2009).
Fleischer Bruce M.
Gschwind Michael K.
Barnie Rexford N
International Business Machines - Corporation
Sai-Halasz George
Tran Jany
Young, Esq. Preston J.
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