Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-07-09
2003-05-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06560733
ABSTRACT:
BACKGROUND
The invention relates generally to digital signal processors and, more particularly, to initialization routines for digital signal processors.
Digital signal processing has become an important technology in the information age. Digital signal processors are utilized in several areas of technology including telecommunications, computers, and telephone answering machines. Generally, digital signal processors may provide digital filtering capabilities that surpass those of analog devices. Conventional digital signal processors include a processing unit, multiple buses, and multiple memory arrays to store data and instructions. Digital signal processors may also include routines to initialize the processor and memory arrays. The initialization routine may be invoked whenever the digital signal processor is powered on or reset. An initialization routine for a digital signal processor may identify errors in the memory arrays due to hardware failures. The initialization routine then stores indications of the failed memory cells in a specified location of the memory array to mark them as bad cells. Once identified, bad memory cells may be avoided during normal operations.
Conventional initialization routines generally do not allow for detection of soft errors in the memory arrays. Soft errors are temporary errors that occur when a bit in a memory array is flipped from a 1 to a 0 or vice versa. For example, soft errors may be due to alpha particles, cosmic rays, or other charged particles. Soft errors may also be caused by defects in manufacturing such as gaps in a cell nitrate layer of a memory cell, also called pinholes, which may reduce the amount of charge that the cell may hold. Additionally, soft errors may be caused by leakage between a memory cell and an adjacent cell, which, over time, may reduce the amount of charge of the memory cell. Soft errors may lead to a loss of data integrity or even memory failure if not detected. Because soft errors are temporary, the affected memory cells need only be marked as failed until the digital signal processor is reset.
When manufacturers of memory array devices perform integration tests with digital signal processors, the detection of hardware errors in the memory arrays is crucial. If a memory array device includes more than a specified number of failed memory cells, the device fails to pass inspection and may not be sold. Because conventional initialization routines do not specifically detect soft errors, any error that is detected is presumed to be due to a hardware failure. Therefore, many memory array devices may fail to pass inspection only because of the presence of temporary soft errors during the integration tests. If an excessive number or memory cells are detected as failed, manufacturers may perform additional tasks to determine whether at least some of the detected errors are soft errors. Such additional testing is time consuming and may increase the cost of electronic systems using digital signal processors.
Thus, it would be beneficial to provide an initialization routine for digital signal processors which detects soft errors.
SUMMARY
In one embodiment, the invention includes an initialization routine for a digital signal processing system that writes a bit pattern to a memory array. The initialization routine may also include the act of reading from the memory array and identifying an error when the value read from a memory cell is different from the value written to a memory cell. Soft errors may be mapped out by storing indications of the failed memory cells at a specified location in the memory array. In another embodiment, the invention provides a digital signal processing system including a memory array coupled to a digital signal processor (DSP) adapted to determine and map out DSP memory array soft errors. The digital signal processing system may also include an initialization routine for detecting and mapping out soft errors. In yet another embodiment, the invention provides a computer system including a processor, a digital signal processor, and a memory array. This embodiment of the invention may also include an initialization routine for the digital signal processor to detect soft errors.
REFERENCES:
patent: 3633175 (1972-01-01), Harper
patent: 4426688 (1984-01-01), Moxley
patent: 4608687 (1986-08-01), Dutton
patent: 4964130 (1990-10-01), Bowden, III et al.
patent: 5199033 (1993-03-01), McGeoch et al.
patent: 5233614 (1993-08-01), Singh
patent: 5357473 (1994-10-01), Mizuno et al.
patent: 5588046 (1996-12-01), Knuth et al.
patent: 5659678 (1997-08-01), Aichelmann, Jr. et al.
patent: 5758056 (1998-05-01), Barr
patent: 5862314 (1999-01-01), Jeddeloh
patent: 5966725 (1999-10-01), Tabo
patent: 5996106 (1999-11-01), Seyyedy
patent: 6256756 (2001-07-01), Faulk, Jr.
patent: 6279128 (2001-08-01), Arnold et al.
patent: 6292869 (2001-09-01), Gerchman et al.
De'cady Albert
Dooley Matthew C.
Micro)n Technology, Inc.
Trop, Pruner&Hu, P.C.
LandOfFree
Soft error detection for digital signal processors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Soft error detection for digital signal processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Soft error detection for digital signal processors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3049520