Soft error detection and correction by 2-dimensional parity

Details Soft error detection and correction by 2-dimensional parity Soft error detection and correction by 2-dimensional parity

2008-05-27

2008-05-27

Louis-Jacques, Jacques (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

07380200

ABSTRACT:
The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

REFERENCES:
patent: 4764927 (1988-08-01), Izumita et al.
patent: 5592499 (1997-01-01), Tanoi
patent: 6216251 (2001-04-01), McGinn

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