Snooping a variable number of cache addresses in a multiple proc

Details Snooping a variable number of cache addresses in a multiple proc Snooping a variable number of cache addresses in a multiple proc

1997-05-14

1999-05-04

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711124, 711138, 711141, 711154, G06F 1200, G06F 1300

Patent

active

059000171

ABSTRACT:
Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

REFERENCES:
patent: 5072369 (1991-12-01), Theus et al.
patent: 5119485 (1992-06-01), Ledbetter et al.
patent: 5193170 (1993-03-01), Lam
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5251310 (1993-10-01), Smelser et al.
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5506971 (1996-04-01), Gullette et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5557769 (1996-09-01), Bailey et al.
patent: 5572701 (1996-11-01), Ishida et al.
patent: 5588131 (1996-12-01), Borrill
patent: 5652859 (1997-07-01), Mulla et al.
patent: 5659710 (1997-08-01), Sherman et al.
patent: 5673414 (1997-09-01), Amini et al.
patent: 5704058 (1997-12-01), Derrick et al.
patent: 5706464 (1998-01-01), Moore et al.
patent: 5708792 (1998-01-01), Hayes et al.
patent: 5715428 (1998-02-01), Wang et al.

Affiliated with

Also associated with

Rating

Snooping a variable number of cache addresses in a multiple proc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Snooping a variable number of cache addresses in a multiple proc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Snooping a variable number of cache addresses in a multiple proc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1867368