Snoop phase in a highly pipelined bus architecture

Details Snoop phase in a highly pipelined bus architecture Snoop phase in a highly pipelined bus architecture

2005-04-12

2005-04-12

Lefkowitz, Sumati (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S105000, C711S146000, C711S169000, C713S400000, C713S600000

Reexamination Certificate

active

06880031

ABSTRACT:
A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

REFERENCES:
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5548733 (1996-08-01), Sarangdhar et al.
patent: 5568620 (1996-10-01), Sarangdhar et al.
patent: 5572703 (1996-11-01), MacWilliams et al.
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5615343 (1997-03-01), Sarangdhar et al.
patent: 5710906 (1998-01-01), Ghosh et al.
patent: 5774700 (1998-06-01), Fisch et al.
patent: 5796977 (1998-08-01), Sarangdhar et al.
patent: 5844858 (1998-12-01), Kyung
patent: 5903738 (1999-05-01), Sarangdhar et al.
patent: 5919254 (1999-07-01), Pawlowski et al.
patent: 5937171 (1999-08-01), Sarangdhar et al.
patent: 5964856 (1999-10-01), Wu et al.
patent: 5978869 (1999-11-01), Gutherie et al.
patent: 5991855 (1999-11-01), Jeddeloh et al.
patent: 5999023 (1999-12-01), Kim
patent: 6012118 (2000-01-01), Jayakumar et al.
patent: 6041380 (2000-03-01), LaBerge
patent: 6065101 (2000-05-01), Gilda
patent: 6092156 (2000-07-01), Schibinger et al.
patent: 6108736 (2000-08-01), Bell
patent: 6272604 (2001-08-01), Nunez et al.
patent: 6405271 (2002-06-01), MacWilliams et al.
patent: 6591321 (2003-07-01), Arimilli et al.
patent: 6609171 (2003-08-01), Singh et al.
patent: 6615323 (2003-09-01), Petersen et al.
patent: 20020059501 (2002-05-01), McKinney et al.
patent: WO 9936858 (1999-07-01), None
Intel Corporation, “Intel Multibus® Specification”, 1978.
Intel Corporation “Multibus® II Bus Architecture Specification Handbook,” 1984.
Intel Corporation, “High-Performance Synchronous 32-Bit Bus: Multibus II,”.
Shanley, Tom, MindShare, Inc. “Pentium® Pro And Pentium® II System Architecture”, Second Edition, PC System Architecture Series, pp. 199-375.
Intel Corporation, “Accelerated Graphics Port Interface Specification,” Revision 1.0, Jul. 31, 1996.
Intel® , Pentium® II Processor Developer's Manual, Chapters 1-6, Oct. 1997.

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