Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-04
2007-12-04
Padmanabhan, Manlo (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S146000, C711S144000, C345S502000
Reexamination Certificate
active
10961749
ABSTRACT:
Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
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Hoover Russell D.
Kriegel Jon K.
Mejdrich Eric O.
Woodward Sandra S.
Padmanabhan Manlo
Patterson & Sheridan LLP
Wang Victor W.
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