Snap-back tolerant integrated circuits

Details Snap-back tolerant integrated circuits Snap-back tolerant integrated circuits

Filed on

2008-12-12

Date issued

2011-12-27

Examiner

Dinh, Son (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Including level shift or pull-up circuit

Other Related Categories

C365S189050

Type

Reexamination Certificate

Status

active

Patent number

08085604

Description

ABSTRACT:
A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF).

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