Smart verify for multi-state memories

Details Smart verify for multi-state memories Smart verify for multi-state memories

2007-07-10

2007-07-10

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

11304961

ABSTRACT:
A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

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