Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent
1997-04-10
1999-10-26
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
709236, G06F 1200
Patent
active
059745185
ABSTRACT:
Disclosed is a network device having a shared memory, a controller for storing Ethernet frames in frame buffers using data chaining to divide up at least the larger frames over a plurality of same sized buffers in the shared memory, wherein there is a tradeoff between using 1) larger buffers capable of receiving more of or all of the larger frames (more wasted buffer space) or 2) smaller buffers requiring more data chaining (wastes processing time to reassemble the frames) and an Ethernet driver having a buffer size adaptation routine which uses an algorithm to dynamically size the buffers. The algorithm records the average frame size during a window of time and uses the average frame size plus an overshoot to reconfigure the buffers' size, when either of the above two stated problems are occurring because the buffer is too large or too small, but with 1) safeguards built into the algorithm to prevent too frequent reconfigurations and 2) the option of including preferences favoring minimization of one of the above stated problems over the other.
REFERENCES:
patent: 5784698 (1998-07-01), Brady et al.
Robbins et al.; Buffered Banks in Multiprocessor Systems; IEEE Transactions on Computers; vol 44, No. 4, Apr. 1995.
Coulter Kenneth R.
Lall Parshotam S.
Milgo Solutions, Inc.
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