Small unit internal verify read in a memory device

Details Small unit internal verify read in a memory device Small unit internal verify read in a memory device

2009-09-02

2011-12-13

Le, Vu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

08077532

ABSTRACT:
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable.

REFERENCES:
patent: 7137050 (2006-11-01), Merritt et al.
Chang Wan Ha, “Program and Sense Operations in a Non-Volatile Memory Device”, U.S. Appl. No. 12/274,508, filed Nov. 20, 2008, 26 pgs.

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