Small skew-clocked synchronous semiconductor device

Details Small skew-clocked synchronous semiconductor device Small skew-clocked synchronous semiconductor device

1994-04-22

1995-05-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365233, 326 66, G11C 700

Patent

active

054208149

ABSTRACT:
In a synchronous semiconductor device, a plurality of input signals having a small amplitude such as an ECL level are converted into a plurality of input signals having a large amplitude such as a CMOS logic level. The large amplitude input signals are held by a plurality of latch circuits and are then supplied to an internal circuit such as a CMOS memory circuit. An ECL level clock signal is converted into CMOS logic level clock signals at a plurality of clock signal conversion circuits. Each of the latch circuits is clocked by the CMOS logic level clock signal generated from one of the clock signal conversion circuits closest thereto.

REFERENCES:
patent: 4583203 (1986-04-01), Monk
patent: 4897820 (1990-01-01), Shiomi et al.
patent: 5287019 (1994-02-01), Nonaka et al.
patent: 5331219 (1994-07-01), Nakamura

Affiliated with

Also associated with

Rating

Small skew-clocked synchronous semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Small skew-clocked synchronous semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Small skew-clocked synchronous semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-367758