Small-sized analog generator producing clock signals

Details Small-sized analog generator producing clock signals Small-sized analog generator producing clock signals

2001-10-30

2004-01-20

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000

Reexamination Certificate

active

06680633

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using an analog oscillator producing clock signals whose frequency is proportional to a control voltage.
BACKGROUND OF THE INVENTION
A prior art generator
10
as shown in
FIG. 1
comprises a frequency divider
12
, a phase comparator
14
, a voltage generator
16
and an oscillator
19
that are series connected. An output OUT of the oscillator
19
is connected to an input of the frequency divider
12
. The generator
10
provides a high-frequency clock signal CKHF (f=FHF) as a function of a reference low-frequency signal CKBF (f=FBF).
The frequency divider
12
receives the high-frequency clock signal CKHF and provides a low-frequency signal CKHF_N that is an image of the signal CKHF, with a frequency equal to f=FHF/N. N is an integer whose value is chosen as a function of the desired frequency FHF
0
for the high-frequency clock signal CKHF, and of the frequency FBF of the reference signal CKBF used: N=FHF
0
/FBF.
The phase comparator
14
has a positive input and a negative input. The signals CKHF_N and CKBF are respectively applied to these inputs. When the signals CKHF_N and CKBF are equal to a 1, the phase comparator
14
determines the phase difference between these signals. This is done by comparing the relative position of the trailing edges of the clock signals CKHF_N and CKBF. The comparator then produces two logic control signals UP, DOWN as a function of the result of the comparison.
The signals UP, DOWN have the following characteristics. If a trailing edge of CKBF is detected first (instants t
1
and t
3
in
FIGS. 2
a
-
2
d
), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase lead over CKHF_N. The comparator
14
then gives an active signal UP which, for example, takes the logic value 1. UP is then deactivated on the next trailing edge of the CKHF_N (instants t
2
and t
4
in
FIGS. 2
a
-
2
d
).
If a trailing edge of CKHF_N is detected first (instants t
5
and t
7
in
FIGS. 2
a
-
2
d
), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase delay with respect to CKHF_N. The comparator
14
then gives an active signal DOWN which, for example, takes the logic value 1. DOWN is then deactivated on the next trailing edge of CKBF (instants t
6
and t
8
in
FIGS. 2
a
-
2
d
). Otherwise, the signals UP and DOWN remain constant, active or inactive as the case may be.
The voltage generator
16
receives the signals UP and DOWN and gives a variable control voltage VCK. The voltage generator
16
comprises a current generator
17
which gives a current ICH from the control signals UP and DOWN. This current ICH has the following characteristics. ICH=+I
0
if UP is active, for example, equal to 1. ICH=−I
0
if DOWN is active, for example, equal to 1. ICH=
0
if UP and DOWN are inactive.
The current ICH is used to charge or discharge a capacitor
18
. When ICH=+I
0
, the capacitor
18
is charged and the voltage VCK at its terminals increases linearly in a slope proportional to I
0
. Conversely, when ICH=−I
0
, the capacitor
18
is discharged and the control voltage VCK at its terminals consequently diminishes linearly in a slope proportional to −I
0
. Naturally, if ICH is zero, the voltage VCK is kept constant.
The variation &Dgr;VCK of the voltage VCK, in terms of absolute value is given by the relationship &Dgr;VCK=I
0
*&Dgr;T
0
/C
0
, where C
0
is the capacitance of the capacitor
18
and &Dgr;T
0
is the duration of a pulse of one of the control signals UP or DOWN.
The pulses UP, DOWN have a maximum duration &Dgr;T
0
max when the signal CKHF has a frequency very distant from its borderline value FHF
0
. This is especially so when the generator
10
is started up. The maximum duration of a pulse UP, DOWN is in the range of the period PBF: &Dgr;T
0
max≈N*PHF
0
.
The oscillator
19
gives the high-frequency clock signal CKHF, whose frequency FHF is proportional to the control voltage VCK. When the control voltage VCK rises, the frequency FHF of the signal CKHF rises, and vice versa. The oscillator
19
has, for example, a looped chain of inverters, made up of an odd number of identical, series connected inverters. The signal CKHF is produced at an output of the last inverter which is connected to an input of the first inverter of the chain. The period PHF of the signal CKHF obtained is directly proportional to the switching time in the inverters which is itself modulated as a function of the control voltage VCK.
The general functioning of the clock signal generator
10
is as follows. If a trailing edge of CKBF is detected first (instants t
1
and t
3
in
FIGS. 2
a
-
2
d
), with the signals CKHF_N, CKBF being previously at a 1, CKBF has a phase lead over CKHF_N. It is estimated in this case that the frequency of the CKHF
13
N is lower than that of CKBF, namely that the frequency of CKHF is lower than the desired value FHF
0
=N*FBF. The comparator
14
then gives an active signal UP, the control voltage VCK rises, as does the frequency of the clock signal CKHF. UP is then deactivated on the next trailing edge of CKHF_N (instants t
2
and t
4
in
FIGS. 2
a
-
2
d
). The duration of the signal UP applied is thus proportional to the phase difference between CKHF_N and CKBF.
Conversely, if a trailing edge of CKHF_N is detected first (instants t
5
in t
7
in
FIGS. 2
a
-
2
d
), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase delay with respect to CKHF_N. In this case, it is estimated that the frequency of CKHF_N is higher than that of CKBF, namely that the frequency of CKHF is higher than the desired value FHF
0
=N*FBF. The comparator
14
then gives an active signal DOWN, and the control voltage VCK diminishes as does the frequency of the clock signal CKHF. DOWN is then deactivated on the next trailing edge of CKBF (instants t
6
and t
8
in
FIGS. 2
a
-
2
d
). The duration of the signal DOWN applied is thus proportional to the phase difference between the signals CKHF_N and CKBF.
When the generator
10
is powered on, the frequency FHF of the signal CKHF is very low. For example, it is equal to the frequency FBF of the reference signal CKBF. The frequency FHF will then vary as a function of the pulses UP, DOWN produced by the phase comparator. The frequency FHF will increase on an average because the pulses UP are more numerous and their duration is greater than that of the pulses DOWN. The frequency FHF will finally converge towards its borderline value FHF
0
. The variations &Dgr;FHF of the frequency FHF are a function of the duration &Dgr;UP, &Dgr;DOWN, of the pulses UP, DOWN, which is itself proportional to the phase difference between the signals CKHF_N and CKBF. It may be recalled that the frequency of CKFH_N is equal to FHF/N.
The control voltage VCK must be limited in amplitude so as to have an acceptable value, especially for the elements forming the oscillator
19
. When the generator
10
is started up, the frequency FHF is low, the period PHF is large and the duration of the pulses UP, DOWN is also large, i.e., close to its maximum value &Dgr;VCKmax. &Dgr;VCKmax is equal to about ICH*N*PHF
0
/C
0
. Consequently, to limit the maximum value &Dgr;VCKmax of the variations in the control voltage VCK, especially when starting, it is necessary to choose a number N that is small or to increase the capacitance C
0
of the capacitor C.
If the frequency of the reference signal CKBF is close to the desired frequency FHF
0
for the clock signal CKHF, i.e., with N in the range of 10 to 50, it is possible to choose a capacitance C
0
that is not excessively large and can be set up in the integrated circuit.
However, if the frequency of the reference signal is low, i.e., far lower than the frequency FHF
0
desired for the clock signal CKHF, th

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