Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-07-20
2002-04-02
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S692000, C438S693000, C438S697000
Reexamination Certificate
active
06365520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to chemical mechanical polishing (CMP) compositions and more particularly to CMP compositions for planarizing shallow trench isolation structures or similar structures for integrated circuits.
2. Discussion of Related Art
The wide spread use of integrated circuits, also known as “chips”, in numerous applications is well known. Typically, integrated circuits are prepared by patterning regions in a substrate such as a silicon or gallium arsenide wafer and patterning layers on the substrate. For example, insulating, conductive and/or semiconductor regions can be patterned in the substrate to produce devices such as transistors, diodes and capacitors.
One method of forming insulating regions in silicon wafers is known as LOCOS (local oxidation of silicon). This method typically involves depositing a silicon nitride layer on the silicon wafer, selectively etching the silicon nitride to expose selected regions of the silicon wafer, and oxidizing the exposed silicon to grow silicon dioxide in the exposed areas. One problem with this method is that silicon dioxide is not only produced in the exposed silicon areas, but also tends to grow laterally under the edges of the silicon nitride layer. Specifically, the silicon dioxide forms “bird's beaks” which project into the silicon wafer underlying the silicon nitride. These bird's beaks negatively affect the operation of the resulting transistor device. Moreover, as the distance between patterned devices continues to decrease in the design of integrated circuits, these bird's beaks could actually connect underneath the silicon nitride layer. As a result, the function of the resulting transistor device could be destroyed.
One alternative to LOCOS is referred to as shallow trench isolation. The shallow trench isolation method does not suffer from the problem of bird's beak formation and thus can be used in small structures. This method typically comprises growing a thin protective silicon dioxide layer, depositing a silicon nitride layer, depositing and patterning a photoresist layer, etching through the exposed areas of the silicon nitride layer and the underlying silicon dioxide into the silicon substrate to a controlled depth, stripping the photoresist layer, depositing a trench fill silicon dioxide, and chemical mechanical polishing the excess trench fill silicon dioxide to expose the covered silicon nitride layer. It is desirable for the thickness of the nitride layer to be consistent across the wafer regardless of the feature size or density in order to achieve consistent performance of the finished devices. Following CMP, the now exposed nitride is stripped leaving regions of silicon for the formation of active devices with insulating trenches formed therebetween.
In the chemical mechanical polishing of these patterned substrates, the local polish rate is known to be dependent on the feature size and the local pattern density. Small isolated structures are removed much more quickly than large structures or densely packed small structures. For this reason, in order to produce a planarized integrated circuit structure, there is a narrow process window, i.e., a small range, of effective polishing times. As a result, it is difficult to produce integrated circuit structures without having some regions which are under-polished and/or over-polished by the CMP process. Under-polishing is characterized by incomplete removal of the silicon dioxide overlying the silicon nitride and prevents the silicon nitride from being properly etched in later process steps. Over-polishing is characterized by the complete removal of the silicon nitride at certain locations and subsequent damage to the silicon wafer at these locations. Both under-polishing and over-polishing result in poor device performance.
One type of CMP slurry currently used in shallow trench isolation methods has high selectivity such that the silicon dioxide is removed by the slurry at a much faster rate than the underlying silicon nitride. These slurries have proven to be effective in removing a blanket silicon dioxide layer deposited over a blanket silicon nitride layer without significantly polishing the silicon nitride layer. However, there is a significant difference between polishing blanket films and patterned wafers. Specifically, the selectivity of the slurry to nitride is significantly different on patterned wafers due to the concentration of force on small isolated features during the CMP process. As a result, these small isolated features are prone to being over-polished even though other features on the same wafer can be at the desired level or even under-polished. Therefore, it is difficult to produce a patterned substrate having uniform silicon nitride thicknesses over the surface of the substrate.
SUMMARY OF THE INVENTION
The present invention provides a CMP composition (slurry) for planarization of integrated structures without under-polishing or over-polishing the materials used in forming these structures. The CMP slurries of this invention effectively planarize raised structures but polish planar structures at a considerably slower rate to prevent over-polishing of these structures. When used for planarization of an integrated structure, the CMP slurry of this invention produces a silicon nitride layer having uniform thickness across the structure thereby maximizing the performance of the corresponding integrated circuit.
Although the description which follows is particularly related to the use of the CMP slurry of this invention for the planarization of shallow trench isolation structures, the CMP slurry may also be used for any metal interconnect structure such as a metal damascene structure comprising a conductive metal (such as Cu, Al, W, Pt, Pd, Au, or any combination or alloy thereof), a barrier or liner layer (such as Ta, TaN, Ti, TiN, TiW, or any combination thereof), and an underlying ILD structure (such as PSG, BPSG, SiO
2
, or any low-K material).
The CMP slurry of this invention comprises small abrasive particles having a mean diameter of between about 2 and 30 nm and large abrasive particles having a mean diameter between 2 and 10 times larger than the mean diameter of the small abrasive particles. Preferably, the large abrasive particles have a mean diameter between about 30 and 100 nm. The small and large abrasive particles are typically silica particles but could be alumina, titania, ceria, germania, silicon carbide, diamond and the like. Preferably, the volume ratio of small abrasive particles to large abrasive particles is between 5:1 and 100:1, and more preferably between 5:1 and 20:1. In addition, the CMP slurry may also contain viscosity additives such as thickening agents, etchants, and other additives (other large abrasive particles). The CMP slurry preferably has a viscosity between about 50 and 500 centipoise.
These features and advantages of the present invention will become more readily apparent to those skilled in the art upon consideration of the following detailed description and accompanying drawings which describe embodiments of the present invention.
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Rhoades Robert L.
Roberts Robert C.
Yancey Paul J.
Benson Kenneth A.
Kaeding Konrad
Kita Gerald K.
Rodel Holdings Inc.
Tran Binh X.
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