Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-06-07
2011-06-07
Rutz, Jared I (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C710S056000
Reexamination Certificate
active
07958312
ABSTRACT:
Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
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Cheng Yu Qing
Glaskowsky Peter N.
Moll Laurent R.
Song Seungyoon Peter
Oracle America Inc.
Osha • Liang LLP
Rutz Jared I
LandOfFree
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