Slurry for chemical mechanical polishing process and method...

Abrasive tool making process – material – or composition – With inorganic material – Metal or metal oxide

Reexamination Certificate

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C051S307000, C051S308000, C106S003000

Reexamination Certificate

active

06626968

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor device using the same, and, more particularly, to a slurry for a chemical mechanical polishing (hereinafter referred to as “CMP”) process that results in a high selectivity ratio to polysilicon and to a method of planarizing the surface of a semiconductor device using the same.
2. Description of the Related Art
The high performance and high integration requirements of modern semiconductor devices demand a multilayer interconnection structure. This multilayer interconnection structure is typically made by performing the sequential steps of film forming/layer deposition followed by an etch process of conductive layers and insulating layers, and repeating these steps several times. Predetermined patterns required for each layer are formed, and then a surface planarization step is performed so that a lithographic process may be easily performed before another pattern is formed.
This planarization step is classified into local planarization and global planarization. The ultimate object of planarization technology is to realize global planarization. Techniques for this global planarization typically include the steps of forming a coating of resin, such as polyimide, followed by an etch-back step, a reflow, and a CMP for the metallic and insulating layers.
A wafer on which a planarization process will be performed is mounted on a rotatory plate, and the surface of the wafer is made to contact a polishing pad. After this, CMP is carried out by rotating the rotatory plate and the polishing pad while providing a supply of slurry between the wafer surface and the polishing pad. In other words, a CMP process is a combination of a chemical action of a slurry, comprising a chemical solution and abrasive grains, and the mechanical action of a polisher. The slurry is supplied between the wafer surface and the polishing pad, and mechanical friction is generated due to the abrasive grains in the slurry and the surface of the pad. As a result of the mechanical effects, the wafer surface is polished. At the same time, part of the wafer surface is removed by the chemical reaction of the chemical components in the slurry with at least portions of the wafer surface.
In general, various kinds of CMP slurries are used depending on the characteristics of the wafer surface materials to be removed. In particular, in a case where a polysilicon layer and a silicon oxide layer are being polished by a CMP method employing a silica-based slurry using silica (SiO
2
) as an abrasive grain, over a given period about twice as much of the polysilicon layer will be removed than the amount of the silicon oxide layer removed. Thus, it can be said that the selectivity ratio of the polysilicon layer to the silicon oxide layer for this CMP process is about 0.5:1. It is therefore difficult or impossible to use a polysilicon layer as a polishing stopping layer when a CMP process is carried out in a specific step of a semiconductor device manufacturing process when using a conventional silica-based slurry. However, for some applications it may be inevitable to carry out such a CMP process despite the problem of the selectivity ratio between a polysilicon layer and a silicon oxide layer in a manufacturing process of a semiconductor device. Alternatively, it may be desirable to use a polysilicon layer as a polishing stopping layer in several steps, not only in a single specific step. Accordingly, it would be desirable to develop a new slurry composition which can be useful in carrying out these types of CMP processes.
OBJECTS OF THE INVENTION
To solve the above problems, it is a general object of the present invention to provide a new slurry composition suitable for a chemical mechanical polishing (CMP) process in which an exposed surface of a material to be polished has the property of hydrophilicity with respect to the slurry.
It is another object of the present invention to provide a method of manufacturing a semiconductor device in which there is a material layer between patterns, and wherein the exposed surface of that material layer has the property of hydrophobicity with respect to the slurry, such that the exposed surface can be globally planarized by a CMP process.
It is still another object of the present invention to provide a method of a manufacturing a semiconductor device where global planarization can be carried out with a CMP process using a material layer as a polishing stopping layer wherein the exposed surface of that layer has the property of hydrophobicity with respect to the slurry.
SUMMARY OF THE INVENTION
Accordingly, to achieve the above objects, there is provided a new slurry composition for a chemical mechanical polishing (CMP) process consisting essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups. The slurry is used for polishing a hydrophilic material, the surface of which is exposed to the slurry in a CMP process. The slurry may further comprise a surfactant and a pH control agent containing acid or base. The polymer additive is at least one member selected from the group consisting of poly vinyl methyl ether (PVME), poly ethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), poly acrylic acid (PM), and poly ether glycol bis ether (PEGBE).
To achieve the above-described objects, there is provided a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In this first embodiment, a first material layer pattern is formed on a lower layer. The surface of the first material layer is then exposed to the slurry according to the present invention and exhibits hydrophobicity during the CMP process. A second material layer is thereafter formed on the entire resultant structure on which the first material layer pattern was formed. The surface of the second material layer is then exposed to the slurry according to the present invention and exhibits hydrophilicity during the CMP process. A CMP process is performed on the second material layer in order to expose at least a portion of the surface of the first material layer using a slurry comprising water, abrasive grains, and polymer additive having both hydrophilic and hydrophobic functional groups. Preferably, in this embodiment of the invention, the first material layer is formed of polysilicon and the second material layer is formed of silicon oxide.
To further achieve the above-described objects, there is provided a method of manufacturing a semiconductor device according to a second embodiment of the present invention. In this second embodiment, an etch mask pattern including a first material layer is formed on a semiconductor substrate. The surface of the etch mask pattern is then exposed to a slurry according to the present invention and exhibits hydrophobicity during the CMP process. A trench is formed to a predetermined depth in the semiconductor substrate using the etch mask pattern as a guide. A second material layer having insularity is thereafter formed on the entire resultant structure where the trench was formed. The surface of the second material layer is then exposed to the slurry according to the present invention and exhibits hydrophilicity during the CMP process. A CMP process is performed on the second material layer in order to expose at least a portion of the surface of the first material layer of the etch mask pattern using the slurry comprising water, abrasive grains, and polymer additive having both hydrophilic and hydrophobic functional groups. The remaining first material layer is then removed.
An anti-reflective layer is further formed on the first material layer of the etch mask pattern, and a first oxide layer is formed between the semiconductor substrate and the first material layer of the etch mask pattern. A thermal oxide layer is formed on the exposed surface of the trench afte

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