Slotted damascene lines for low resistive wiring lines for...

Details Slotted damascene lines for low resistive wiring lines for... Slotted damascene lines for low resistive wiring lines for...

1998-11-30

2001-07-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C257S758000

Reexamination Certificate

active

06265308

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits (ICs), and more particularly to a structure and method for forming wiring lines for the integrated circuits and relates to an interconnect scheme forming an additional type of metal lines without additional mask levels.
2. Description of the Related Art
In DRAM circuits, the need for multiple metal levels is driven by the requirement to increase the array efficiency with increasing memory size. Three metal levels are conventionally used as bitline, master or stitched wordline and column select lines.
Recently, several hybrid or hierarchical bitline architectures have been proposed in order to decrease the number of sense amplifiers. These architectures require an additional metal level. Simultaneously, DRAM support circuits also need multiple wiring levels for area reduction. Low resistance is the main requirement for the support circuits, in particular for power bussing.
By the same token, low capacitance is important for the use as bitlines or master bitlines in the array.
Conventional interconnection architecture for integrated circuits typically includes horizontal lines of various materials (e.g., metal silicides, W, Al , Cu, and the like), and vertical vias between the horizontal interconnect levels (e.g., M
1
, M
2
wiring levels which are horizontal).
The vias are typically etched into the interlevel dielectric (ILD) formed, for example, of SiO
2
, and subsequently are filled by chemical vapor deposition (CVD) or plasma vapor deposition (PVD) metal such as, for example, W, Al, Cu, and the like.
Thus, conventionally linear and circular patterns are defined by lithography and etching for the horizontal (HI) and vertical (VI) interconnect levels, respectively, and the vertical interconnect levels (VI) are limited to vias.
The resistance of metal lines is defined by height, width and resistivity. The height is often limited by arrays of smallest feature size (e.g., memory arrays). Due to capacitance and space minimization in these areas, the height of the metal lines is strongly limited. On the other hand, the use of lines with large line width leads to an increased chip size. Consequently, the resistance of metal lines is globally restricted to values which do not allow for high current densities due to Joule heating of highly, resistive lines.
Thus, power bus lines, designed to carry high current densities, and signal or equipotential lines that do not allow a large potential gradient along the line, are typically designed on an additional metal level using a thicker metal height, or using broad or parallel lines on thin metal levels, thereby increasing chip size.
Hence, if thicker metal lines are desired for increased current capacity (and thus higher bus speeds for example), then the conventional techniques for producing thick metal lines include increasing the thickness of the metal layer and increasing the number of metal layers, each of which increases chip size and processing steps.
Moreover, for a given combination of conducting and insulating materials, the only way to significantly reduce the capacitance of metal lines with narrow spacing is to make the metal stack sufficiently thin. Similarly, low resistance lines are produced by increasing their thickness accordingly. However, conventionally, both characteristics cannot be united on one metal level.
In a typical multi-layer metallization sequence, thin metal layers (e.g., bitline levels for DRAMs) are built first and then thick ones are built last. Consequently, the first metal levels are not useful for low resistance requirements. This has resulted in a significant limitation for a chip-size-optimized interconnect design. Moreover, the tradeoff between low capacitance and low resistance requirements is enhanced when the number of thin metal layers is increased as proposed recently for multiple bitline architectures.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems and drawbacks of the conventional structures and method, an object of the present invention is to provide a structure and method for producing integrated circuits having multilayers (≧2) of metallization.
Another object is to simultaneously define linear features on a vertical interconnect level (C
1
) in addition to the circular vertical interconnects.
Yet another object is to form a low resistive horizontal interconnect (HI) with a height of the interlayer dielectric level (ILD) thickness.
Still another object of the present invention is to make vertical level interconnects with slotted lines.
In a first aspect, a method according to the present invention for forming interlayer wiring in a semiconductor interlayer dielectric, includes simultaneously patterning a via and a slotted line in the interlayer dielectric, simultaneously etching the via and the slotted line; and simultaneously filling the via and the slotted lines with a metal.
In a second aspect, a method of forming a metal wiring in a semiconductor device, according to the present invention, includes simultaneously defining a linear feature on a vertical interconnect level and a vertical interconnect in a substrate of the semiconductor device, simultaneously forming a line and a via in the substrate, simultaneously etching the line and the via, simultaneously filling the line and the via with a metal, to form the linear feature and the vertical interconnect, and planarizing the linear feature and the vertical interconnect.
The present invention realizes thick metal lines for high current and low potential gradient purposes by extending vias (e.g., vertical interconnects) to lines (horizontal interconnects) with no increase in process cost and a savings in chip size. The concept of slotted lines can be applied to different layers such as, for example, CG (contact-to-gate), CD (contact-to-diffusion layer) and C
1
(contact between metals).
Moreover, slots and vias can be formed simultaneously with the same depth. Both features are positioned between two given levels of horizontal metal wires (e.g., M
0
and M
1
). The vias are vertical interconnects, but the slots are horizontal interconnects with a resistivity much lower than M
0
or M
1
. In addition to the formation of the slots, for example, between M
0
and M
1
, another lithography and etch step will be used to define the upper metal level M
1
.
Hence, the present invention forms vias and line and obtains the additional feature of a low resistivity interconnect by combining circular and linear features on one mask (e.g., using a same mask). Thus, the invention forms a relatively thick wire out of the combined metal and via troughs in a dual damascene process. With the relatively thicker wire, a higher current (and thus a higher speed data bus) can be used.
Hence, the invention provides a processing which allows the formation of both, low capacitance metallization (e.g., in an array of lines) and low resistance metallization (e.g., in support circuits) simultaneously and without increasing cost or complexity.
Further, it will not be necessary to contact the M
0
level, and indeed the underlying M
0
could be eliminated.
Thus, the invention results in the capability of using a higher current without increasing the number of metal layers (e.g., non-increase in process cost) and chip size. Thus, there will be an increase in the dies per wafer.
Moreover, the present invention provides a unique method which allows building simultaneously thin and thick metal lines without adding any extra layers.
A key feature of the process is extending vias, which are conventionally used for vertical interconnects into lines that serve now as low resistance horizontal interconnects. These “slotted vias” can be capped with a line of the subsequent metal level (M
1
) and can fully land on a metal line formed on the preceding metal level (M
0
). Thus, the total metal height extends from the bottom of M
0
to the top of M
1
and in a preferred implementation may amount to a total height of about 900 nm.
In one implement

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