Sliced crossbar architecture with no inter-slice communication

Details Sliced crossbar architecture with no inter-slice communication Sliced crossbar architecture with no inter-slice communication

2007-09-25

2007-09-25

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C370S389000

Reexamination Certificate

active

11514854

ABSTRACT:
A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

REFERENCES:
patent: 5689506 (1997-11-01), Chiussi et al.

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