Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2007-04-04
2008-12-30
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S087000
Reexamination Certificate
active
07471111
ABSTRACT:
A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor.
REFERENCES:
patent: 2001/0045508 (2001-11-01), Dierickx
patent: 2004/0165449 (2004-08-01), Pan
Goel Ankush
Seth Sumantra
Brady III Wade J.
Cho James H.
Franz Warren L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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