Slew rate control circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity

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326 27, 326 83, 326 29, 327170, H03K 1716, H03K 19003, H03K 512

Patent

active

06075379&

ABSTRACT:
Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

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T. Gabara, W. Fischer, J. Harrington, W. Troutman, Forming Damped LRC Parasitic Circuits In Simultaneously Switched CMOS Output Buffers, IEEE Journal Of Solid-State Circuits, vol. 32, No. 3, Mar. 1997, pp. 407-417.

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