Slew rate calibrating circuit and slew rate calibrating method

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

Reexamination Certificate

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Details

C327S172000, C327S170000, C327S178000, C326S027000

Reexamination Certificate

active

11362819

ABSTRACT:
A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

REFERENCES:
patent: 7109768 (2006-09-01), Rashid
patent: 2005/0285648 (2005-12-01), Wilson et al.
patent: 2007/0001725 (2007-01-01), Atha et al.
patent: 2000-174594 (2000-06-01), None
patent: 2002-26712 (2002-01-01), None

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