Sleep transistor array apparatus and method with leakage...

Details Sleep transistor array apparatus and method with leakage... Sleep transistor array apparatus and method with leakage...

2006-12-12

2010-10-12

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

C326S040000, C326S034000, C327S544000, C365S227000

Reexamination Certificate

active

07812631

ABSTRACT:
In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

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