Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-19
2001-02-06
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06185720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of digital circuitry. More particularly, this invention relates to slaveless synchronous system design.
2. Background
Computer technology is continually progressing, providing more and more computing power in continually smaller packages. One method employed to obtain this increased power is to place more and more components onto a single integrated circuit (IC) chip. This can be accomplished by reducing the size of the individual components as well as reducing the number of components required to perform various functions. Many of the components on an IC are controlled or “clocked” by a clock signal and are commonly referred to as synchronous components. In general, the clock signal in a device is used to identify when signals are to be transferred between devices.
One component which is commonly used in a wide variety of ICs is a latch. A latch typically stores a single bit of data and is typically controlled by a clock signal. Different types of latches exist which can be used in ICs, including pulse latches and single- and two-phase latches.
It is beneficial to use single- or two-phase latches in some situations, such as when a designer wishes to use the benefits of time borrowing across phases of a clock cycle. However, some problems do exist with their use. One such problem is power consumption. Because there are two portions to the single- and two-phase latches, each activated by different phases of a clock signal, two different types of clock signals must be routed to each of the single- and two-phase latches on the IC. An additional problem is that of clock skew. By requiring the routing of an additional clock signal for the second portion of the latch, as well as the additional load on the clock signal line caused by the second portion of the latch, the skew of the clock signal is increased. Thus, it would be beneficial to provide a way to reduce the effects of the problems associated with using single- and two-phase latches.
As will be described in more detail below, the present invention provides a slaveless synchronous system design that achieves these and other desired results which will be apparent to those skilled in the art from the description to follow.
SUMMARY OF THE INVENTION
A slaveless synchronous system design is described herein. A method is described which checks whether a propagation delay of a data path is longer than a particular time duration. If the propagation delay of the data path is longer than the particular time duration, then a slave latch of a master/slave flip-flop is removed from the data path.
An apparatus is described which includes a master latch of a master/slave flip-flop, wherein the master latch includes a first data output. The apparatus also includes a logic coupled to receive the first data output, wherein the logic includes a second data output without using a slave latch of a master/slave flip-flop, and a non-slave latch coupled to receive the second data output.
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Yuan et al. (“New single-clock CMOS latches and flipflops with improved speed and power savings”, IEEE Journal of Solid-State Circuits, vol. 32, No. 1, Jan. 1997, pp. 62-69).
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kik Phallaka
Lintz Paul R.
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